公开(公告)号：US08835328B2

公开(公告)日：2014-09-16

申请号：US13763399

申请日：2013-02-08

Applicant: Globalfoundries, Inc.

Inventor： Wontae Hwang ,  Il Goo Kim ,  Dae-Han Choi ,  Sang Cheol Han

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L29/66795 ,  Y10S438/946 ,  Y10S438/947

Abstract: Methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes providing a mandrel layer overlying a semiconductor substrate and patterning the mandrel layer into mandrel structures. The method further includes forming a protective layer between the mandrel structures. Spacers are formed around each of the mandrel structures and overlying the protective layer to define exposed regions of the protective layer and covered regions of the protective layer. The exposed regions of the protective layer are etched using the spacers and the mandrel structures as a mask. The spacers are removed from the covered regions of the protective layer. The covered regions of the protective layer form mask segments for etching the semiconductor substrate. The method removes the mandrel structures and etches the semiconductor substrate exposed between mask segments to form semiconductor fin structures.

Abstract translation: 本文提供了用于制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供覆盖在半导体衬底上的心轴层，并将心轴层图案化成心轴结构。 该方法还包括在心轴结构之间形成保护层。 间隔件形成在每个心轴结构周围并且覆盖保护层以限定保护层的暴露区域和保护层的覆盖区域。 使用间隔件和心轴结构作为掩模来蚀刻保护层的暴露区域。 从保护层的覆盖区域移除间隔物。 保护层的覆盖区域形成用于蚀刻半导体衬底的掩模段。 该方法去除芯棒结构并蚀刻暴露在掩模段之间的半导体衬底以形成半导体鳍结构。

公开(公告)号：US20140227879A1

公开(公告)日：2014-08-14

申请号：US13763399

申请日：2013-02-08

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Wontae Hwang ,  IL Goo Kim ,  DAE-HAN Choi ,  Sang Cheol Han

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  H01L29/66795 ,  Y10S438/946 ,  Y10S438/947

Abstract: Methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes providing a mandrel layer overlying a semiconductor substrate and patterning the mandrel layer into mandrel structures. The method further includes forming a protective layer between the mandrel structures. Spacers are formed around each of the mandrel structures and overlying the protective layer to define exposed regions of the protective layer and covered regions of the protective layer. The exposed regions of the protective layer are etched using the spacers and the mandrel structures as a mask. The spacers are removed from the covered regions of the protective layer. The covered regions of the protective layer form mask segments for etching the semiconductor substrate. The method removes the mandrel structures and etches the semiconductor substrate exposed between mask segments to form semiconductor fin structures.

Abstract translation: 本文提供了用于制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供覆盖在半导体衬底上的心轴层，并将心轴层图案化成心轴结构。 该方法还包括在心轴结构之间形成保护层。 间隔件形成在每个心轴结构周围并且覆盖保护层以限定保护层的暴露区域和保护层的覆盖区域。 使用间隔件和心轴结构作为掩模来蚀刻保护层的暴露区域。 从保护层的覆盖区域移除间隔物。 保护层的覆盖区域形成用于蚀刻半导体衬底的掩模段。 该方法去除芯棒结构并蚀刻暴露在掩模段之间的半导体衬底以形成半导体鳍结构。

公开(公告)号：US08993445B2

公开(公告)日：2015-03-31

申请号：US13740343

申请日：2013-01-14

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Dae-Han Choi ,  Dae Geun Yang ,  Chang Ho Maeng ,  Wontae Hwang

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311 ,  B44C1/22 ,  C25F3/00 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L29/40

CPC classification number: H01L29/401 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods are provided for facilitating fabricating a semiconductor device by selectively etching a gate structure sidewall(s) to facilitate subsequent sidewall spacer isolation. The method includes, for instance: providing a gate structure with a protective layer(s) over the gate structure, the gate structure including one or more sidewalls; selectively removing a portion of the gate structure along at least one sidewall to partially undercut the protective layer(s); and forming a sidewall spacer(s) over the sidewall(s) of the gate structure, with a portion of the sidewall spacer at least partially filling the partial undercut of the protective layer(s), and residing below the protective layer(s). In certain embodiments, the selectively removing includes implanting the sidewall(s) with a dopant to produce a doped region(s) of the gate structure, and subsequently, at least partially removing the doped region(s) of the gate structure selective to an undoped region of the gate structure.

Abstract translation: 提供了通过选择性地蚀刻栅极结构侧壁以促进随后的侧壁间隔隔离来促进制造半导体器件的方法。 该方法包括例如：在栅极结构上提供具有保护层的栅极结构，栅极结构包括一个或多个侧壁; 沿着至少一个侧壁选择性地去除所述栅极结构的一部分以部分地切割所述保护层; 以及在所述栅极结构的侧壁上形成侧壁间隔物，所述侧壁间隔物的一部分至少部分地填充所述保护层的部分底切，并且位于所述保护层的下方， 。 在某些实施例中，选择性去除包括用掺杂剂注入侧壁以产生栅极结构的掺杂区域，并且随后至少部分地去除栅极结构的掺杂区域， 栅极结构的未掺杂区域。