公开(公告)号：US20190244650A1

公开(公告)日：2019-08-08

申请号：US15889369

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Akhilesh Jaiswal ,  Ajey P. Jacob ,  Bipul C. Paul ,  William Taylor ,  Danny Pak-Chum Shum

IPC: G11C11/16 ,  H01L43/08 ,  H01L27/22

Abstract: A magneto-resistive memory (MRM) structure includes a source line and a first transistor that includes a source region and a drain region. The source line is electrically connected to the source region of the first transistor. The MRM structure further includes an MRM cell that includes an MRM transistor electrically in series with an MRM magnetic tunnel junction (MTJ). The MRM transistor is electrically connected to the drain region of the first transistor such that the MRM cell is electrically in series with the first transistor. Still further, the MRM structure further includes a voltage amplifier electrically connected to a mid-point node of the first transistor and the MRM transistor, a sense-amplifier electrically connected to the voltage amplifier, and a bit line electrically connected to the MRM MTJ of the MRM cell.

公开(公告)号：US10510392B1

公开(公告)日：2019-12-17

申请号：US16047882

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Bipul C. Paul ,  Akhilesh Jaiswal ,  Ajey Poovannummoottil Jacob ,  William Taylor ,  Danny Pak-Chum Shum

IPC: G11C11/16

Abstract: Integrated circuits, memory arrays and methods for operating integrated circuit devices are provided. In an embodiment, an integrated circuit includes a selected column of bit cells, wherein each bit cell in the selected column is coupled to a source line and coupled to a bit line. Further, the integrated circuit includes a first column of bit cells laterally adjacent the selected column, wherein each bit cell in the first column is coupled to the source line. Also, the integrated circuit includes a second column of bit cells laterally adjacent the selected column, wherein each bit cell in the second column is coupled to the bit line.

公开(公告)号：US10468083B1

公开(公告)日：2019-11-05

申请号：US16010841

申请日：2018-06-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Akhilesh Jaiswal ,  Ajey Poovannummoottil Jacob

IPC: G11C5/06 ,  G11C11/16 ,  H01L43/02 ,  H01F10/32 ,  H01L43/12 ,  H01L43/10

Abstract: Integrated circuits and methods of operating and producing the same are provided. In an exemplary embodiment, an integrated circuit includes a look up table with a first and second memory cell. The first memory cell includes a first magneto electric (ME) layer, a first free layer adjacent to the first ME layer, and a first fixed layer. The second memory cell includes a second ME layer, a second free layer adjacent to the second ME layer, and a second fixed layer. A first word line is in direct communication with the first and second free layers, wherein direct communication is a connection through zero, one, or more intervening components that are electrical conductors. A first bit line is in direct communication with the first ME layer, and a second bit line is in direct communication with the second ME layer.

公开(公告)号：US10515679B2

公开(公告)日：2019-12-24

申请号：US15889369

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Akhilesh Jaiswal ,  Ajey P. Jacob ,  Bipul C. Paul ,  William Taylor ,  Danny Pak-Chum Shum

IPC: G11C11/00 ,  G11C11/16 ,  H01L27/22 ,  H01L43/08

Abstract: A magneto-resistive memory (MRM) structure includes a source line and a first transistor that includes a source region and a drain region. The source line is electrically connected to the source region of the first transistor. The MRM structure further includes an MRM cell that includes an MRM transistor electrically in series with an MRM magnetic tunnel junction (MTJ). The MRM transistor is electrically connected to the drain region of the first transistor such that the MRM cell is electrically in series with the first transistor. Still further, the MRM structure further includes a voltage amplifier electrically connected to a mid-point node of the first transistor and the MRM transistor, a sense-amplifier electrically connected to the voltage amplifier, and a bit line electrically connected to the MRM MTJ of the MRM cell.