公开(公告)号：US09053923B2

公开(公告)日：2015-06-09

申请号：US14072149

申请日：2013-11-05

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Azat Latypov ,  Edward Teoh Kah Ching ,  He Yi

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/027

CPC classification number: H01L21/0271 ,  G03F7/0002 ,  H01L21/308 ,  H01L21/3081

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming etch resistant fill control topographical features that overlie a semiconductor substrate. The etch resistant fill control topographical features define an etch resistant fill control confinement well. A block copolymer is deposited into the etch resistant fill control confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant fill control topographical features direct the etch resistant phase to form an etch resistant plug in the etch resistant fill control confinement well.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括形成覆盖半导体衬底的耐蚀刻填充控制形貌特征。 抗蚀刻填充控制形貌特征限定了耐蚀刻填充控制密封阱。 将嵌段共聚物沉积到耐蚀刻填充控制密封阱中。 嵌段共聚物被相分离成可蚀刻相和耐蚀刻相。 耐蚀刻填充控制形状特征指示耐蚀刻相，以在耐蚀刻填充控制密封阱中形成耐蚀刻塞。

公开(公告)号：US20150126034A1

公开(公告)日：2015-05-07

申请号：US14072149

申请日：2013-11-05

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Azat Latypov ,  Edward Teoh Kah Ching ,  He Yi

IPC: H01L21/02 ,  H01L21/306

CPC classification number: H01L21/0271 ,  G03F7/0002 ,  H01L21/308 ,  H01L21/3081

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming etch resistant fill control topographical features that overlie a semiconductor substrate. The etch resistant fill control topographical features define an etch resistant fill control confinement well. A block copolymer is deposited into the etch resistant fill control confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant fill control topographical features direct the etch resistant phase to form an etch resistant plug in the etch resistant fill control confinement well.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括形成覆盖半导体衬底的耐蚀刻填充控制形貌特征。 抗蚀刻填充控制形貌特征限定了耐蚀刻填充控制密封阱。 将嵌段共聚物沉积到耐蚀刻填充控制密封阱中。 嵌段共聚物被相分离成可蚀刻相和耐蚀刻相。 耐蚀刻填充控制形状特征指示耐蚀刻相，以在耐蚀刻填充控制密封阱中形成耐蚀刻塞。