公开(公告)号：US20150076560A1

公开(公告)日：2015-03-19

申请号：US14030104

申请日：2013-09-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Joanna Wasyluk ,  Carsten Reichel ,  Joachim Patzer ,  Kai Wurster

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02694 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/092 ,  H01L29/66636

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a cavity in a semiconductor region laterally adjacent to a gate electrode structure. An EPI strain-inducing fill is deposited into the cavity. The EPI strain-inducing fill includes a main SiGe layer and a Si cap that overlies the main SiGe layer. The EPI strain-inducing fill is doped with boron and has a first peak boron content in an upper portion of the EPI strain-inducing fill of about 2.5 times or greater than an average boron content in an intermediate portion of the main SiGe layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，用于制造集成电路的方法包括在与栅电极结构相邻的半导体区域中形成空腔。 将EPI应变诱导填充物沉积到空腔中。 EPI应变诱导填料包括主SiGe层和覆盖在主SiGe层上的Si盖。 EPI应变诱导填充物掺杂硼，并且在EPI应变诱导填料的上部具有在主SiGe层的中间部分中的平均硼含量的约2.5倍或更大的第一峰硼含量。

公开(公告)号：US09064961B2

公开(公告)日：2015-06-23

申请号：US14030104

申请日：2013-09-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Joanna Wasyluk ,  Carsten Reichel ,  Joachim Patzer ,  Kai Wurster

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02694 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/092 ,  H01L29/66636

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a cavity in a semiconductor region laterally adjacent to a gate electrode structure. An EPI strain-inducing fill is deposited into the cavity. The EPI strain-inducing fill includes a main SiGe layer and a Si cap that overlies the main SiGe layer. The EPI strain-inducing fill is doped with boron and has a first peak boron content in an upper portion of the EPI strain-inducing fill of about 2.5 times or greater than an average boron content in an intermediate portion of the main SiGe layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，用于制造集成电路的方法包括在与栅电极结构相邻的半导体区域中形成空腔。 将EPI应变诱导填充物沉积到空腔中。 EPI应变诱导填料包括主SiGe层和覆盖在主SiGe层上的Si盖。 EPI应变诱导填充物掺杂硼，并且在EPI应变诱导填料的上部具有在主SiGe层的中间部分中的平均硼含量的约2.5倍或更大的第一峰硼含量。