公开(公告)号：US20150076560A1

公开(公告)日：2015-03-19

申请号：US14030104

申请日：2013-09-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Joanna Wasyluk ,  Carsten Reichel ,  Joachim Patzer ,  Kai Wurster

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02694 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/092 ,  H01L29/66636

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a cavity in a semiconductor region laterally adjacent to a gate electrode structure. An EPI strain-inducing fill is deposited into the cavity. The EPI strain-inducing fill includes a main SiGe layer and a Si cap that overlies the main SiGe layer. The EPI strain-inducing fill is doped with boron and has a first peak boron content in an upper portion of the EPI strain-inducing fill of about 2.5 times or greater than an average boron content in an intermediate portion of the main SiGe layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，用于制造集成电路的方法包括在与栅电极结构相邻的半导体区域中形成空腔。 将EPI应变诱导填充物沉积到空腔中。 EPI应变诱导填料包括主SiGe层和覆盖在主SiGe层上的Si盖。 EPI应变诱导填充物掺杂硼，并且在EPI应变诱导填料的上部具有在主SiGe层的中间部分中的平均硼含量的约2.5倍或更大的第一峰硼含量。

公开(公告)号：US09064961B2

公开(公告)日：2015-06-23

申请号：US14030104

申请日：2013-09-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Joanna Wasyluk ,  Carsten Reichel ,  Joachim Patzer ,  Kai Wurster

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02694 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/092 ,  H01L29/66636

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a cavity in a semiconductor region laterally adjacent to a gate electrode structure. An EPI strain-inducing fill is deposited into the cavity. The EPI strain-inducing fill includes a main SiGe layer and a Si cap that overlies the main SiGe layer. The EPI strain-inducing fill is doped with boron and has a first peak boron content in an upper portion of the EPI strain-inducing fill of about 2.5 times or greater than an average boron content in an intermediate portion of the main SiGe layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，用于制造集成电路的方法包括在与栅电极结构相邻的半导体区域中形成空腔。 将EPI应变诱导填充物沉积到空腔中。 EPI应变诱导填料包括主SiGe层和覆盖在主SiGe层上的Si盖。 EPI应变诱导填充物掺杂硼，并且在EPI应变诱导填料的上部具有在主SiGe层的中间部分中的平均硼含量的约2.5倍或更大的第一峰硼含量。

公开(公告)号：US20130113019A1

公开(公告)日：2013-05-09

申请号：US13663589

申请日：2012-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Carsten Reichel ,  Thorsten Kammler ,  Annekathrin Zeun ,  Stephan Kronholz

IPC: H01L29/78 ,  H01L27/092

CPC classification number: H01L29/78 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823481 ,  H01L27/092

Abstract: Generally, the subject matter disclosed herein is directed to semiconductor devices with reduced threshold variability having a threshold adjusting semiconductor material in the device active region. One illustrative semiconductor device disclosed herein includes an active region in a semiconductor layer of a semiconductor device substrate, the active region having a region length and a region width that are laterally delineated by an isolation structure. The semiconductor device further includes a threshold adjusting semiconductor alloy material layer that is positioned on the active region substantially without overlapping the isolation structure, the threshold adjusting semiconductor alloy material layer having a layer length that is less than the region length. Additionally, the disclosed semiconductor device includes a gate electrode structure that is positioned above the threshold adjusting semiconductor alloy material layer, the gate electrode structure including a high-k dielectric material and a metal-containing electrode material formed above the high-k dielectric material.

Abstract translation: 通常，本文公开的主题涉及具有阈值可变性降低的半导体器件，其具有在器件有源区域中的阈值调节半导体材料。 本文公开的一个说明性的半导体器件包括在半导体器件衬底的半导体层中的有源区，该有源区具有由隔离结构横向描绘的区域长度和区域宽度。 所述半导体器件还包括阈值调节半导体合金材料层，所述阈值调节半导体合金材料层基本上不与所述隔离结构重叠地位于所述有源区上，所述阈值调节半导体合金材料层具有小于所述区域长度的层长度。 此外，所公开的半导体器件包括位于阈值调节半导体合金材料层上方的栅电极结构，该栅电极结构包括形成在高k电介质材料上方的高k电介质材料和含金属电极材料。

公开(公告)号：US08674416B2

公开(公告)日：2014-03-18

申请号：US13663589

申请日：2012-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Carsten Reichel ,  Thorsten Kammler ,  Annekathrin Zeun ,  Stephan Kronholz

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/78 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823481 ,  H01L27/092

Abstract: Generally, the subject matter disclosed herein is directed to semiconductor devices with reduced threshold variability having a threshold adjusting semiconductor material in the device active region. One illustrative semiconductor device disclosed herein includes an active region in a semiconductor layer of a semiconductor device substrate, the active region having a region length and a region width that are laterally delineated by an isolation structure. The semiconductor device further includes a threshold adjusting semiconductor alloy material layer that is positioned on the active region substantially without overlapping the isolation structure, the threshold adjusting semiconductor alloy material layer having a layer length that is less than the region length. Additionally, the disclosed semiconductor device includes a gate electrode structure that is positioned above the threshold adjusting semiconductor alloy material layer, the gate electrode structure including a high-k dielectric material and a metal-containing electrode material formed above the high-k dielectric material.

Abstract translation: 通常，本文公开的主题涉及具有阈值可变性降低的半导体器件，其具有在器件有源区域中的阈值调节半导体材料。 本文公开的一个说明性的半导体器件包括在半导体器件衬底的半导体层中的有源区，该有源区具有由隔离结构横向描绘的区域长度和区域宽度。 所述半导体器件还包括阈值调节半导体合金材料层，所述阈值调节半导体合金材料层基本上不与所述隔离结构重叠地位于所述有源区上，所述阈值调节半导体合金材料层具有小于所述区域长度的层长度。 此外，所公开的半导体器件包括位于阈值调节半导体合金材料层上方的栅电极结构，该栅电极结构包括形成在高k电介质材料上方的高k电介质材料和含金属电极材料。

公开(公告)号：US20130307090A1

公开(公告)日：2013-11-21

申请号：US13948672

申请日：2013-07-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephan Kronholz ,  Thorsten Kammler ,  Gunda Beernink ,  Carsten Reichel

IPC: H01L29/161

CPC classification number: H01L29/161 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: The threshold voltage of a sophisticated transistor may be adjusted by providing a specifically designed semiconductor alloy in the channel region of the transistor, wherein a negative effect of this semiconductor material with respect to inducing a strain component in the channel region may be reduced or over-compensated for by additionally incorporating a strain-adjusting species. For example, a carbon species may be incorporated in the channel region, the threshold voltage of which may be adjusted on the basis of a silicon/germanium alloy of a P-channel transistor. Consequently, sophisticated metal gate electrodes may be formed in an early manufacturing stage.

Abstract translation: 可以通过在晶体管的沟道区域中提供特别设计的半导体合金来调整复杂晶体管的阈值电压，其中该半导体材料相对于在沟道区域中诱导应变分量的负面影响可以被减小或过量， 通过另外结合应变调节物种来补偿。 例如，可以在沟道区域中引入碳物质，其阈值电压可以基于P沟道晶体管的硅/锗合金来调节。 因此，可以在早期制造阶段形成复杂的金属栅电极。