公开(公告)号：US20140183720A1

公开(公告)日：2014-07-03

申请号：US13731305

申请日：2012-12-31

Applicant: GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Scott Beasor ,  Jay Strane ,  Man Fai Ng ,  Brett H. Engel ,  Chang Yong Xiao ,  Michael P. Belyansky ,  Tsung-Liang Chen ,  Kyung Bum Koo

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/48 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Methods of manufacturing semiconductor integrated circuits having a compressive nitride layer are disclosed. In one example, a method of fabricating an integrated circuit includes depositing an aluminum layer over a semiconductor substrate, depositing a tensile silicon nitride layer or a neutral silicon nitride layer over the aluminum layer, and depositing a compressive silicon nitride layer over the tensile silicon nitride layer or the neutral silicon nitride layer. The compressive silicon nitride layer is deposited at a thickness that is at least about twice a thickness of the tensile silicon nitride layer or the neutral silicon nitride layer. Further, there is no delamination present at an interface between the aluminum layer and the tensile silicon nitride layer or the neutral silicon nitride layer, or at an interface between tensile silicon nitride layer or the neutral silicon nitride layer and the compressive nitride layer.

Abstract translation: 公开了具有压缩氮化物层的半导体集成电路的制造方法。 在一个示例中，制造集成电路的方法包括在半导体衬底上沉积铝层，在铝层上沉积拉伸氮化硅层或中性氮化硅层，以及在抗拉氮化硅上沉积压缩氮化硅层 层或中性氮化硅层。 压缩氮化硅层以至少约为拉伸氮化硅层或中性氮化硅层厚度的约两倍的厚度沉积。 此外，在铝层和拉伸氮化硅层或中性氮化硅层之间的界面处，或者在拉伸氮化硅层或中性氮化硅层与压缩氮化物层之间的界面处没有分层存在。

公开(公告)号：US20130249000A1

公开(公告)日：2013-09-26

申请号：US13898033

申请日：2013-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bin Yang ,  Man Fai Ng

IPC: H01L29/78 ,  H01L27/092

CPC classification number: H01L29/7816 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833

Abstract: A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions in the substrate, forming halo regions under the source/drain extension regions, after forming the source drain regions, and forming a gate electrode on the substrate between the source/drain regions. By forming the halo regions after the high temperature processing involved informing the source/drain and source/drain extension regions, halo diffusion is minimized, thereby maintaining sufficient distance between halo regions and reducing short channel NMOS Vt roll-off.

Abstract translation: 短沟道半导体器件形成有与栅电极的底部彼此分离的晕圈。 实施例包括在形成源极/漏极区域和源极/漏极延伸区域之后注入晕圈。 一个实施例包括在衬底中形成源极/漏极延伸区域，在衬底中形成源极/漏极区域，在形成源极漏极区域之后在源极/漏极延伸区域下方形成卤素区域，以及在衬底上形成栅极电极 源/漏区。 通过在涉及源极/漏极和源极/漏极延伸区域的高温处理之后形成晕圈区域，使得光晕扩散最小化，从而在晕圈区域之间保持足够的距离并且减少短沟道NMOS Vt滚降。

公开(公告)号：US08674438B2

公开(公告)日：2014-03-18

申请号：US13765474

申请日：2013-02-12

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Bin Yang ,  Man Fai Ng

IPC: H01L29/04

CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a gate structure overlying a region of semiconductor material, wherein the width of the gate structure is aligned with a crystal direction of the semiconductor material. The method continues by forming recesses about the gate structure and forming a stress-inducing semiconductor material in the recesses.

Abstract translation: 提供了半导体器件结构和相关制造方法的装置。 制造半导体器件结构的一种方法包括形成覆盖半导体材料区域的栅极结构，其中栅极结构的宽度与半导体材料的<100>晶体方向对齐。 该方法通过在栅极结构周围形成凹槽并在凹部中形成应力诱导半导体材料来继续。