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    Methods of forming group III-V semiconductor materials on group IV substrates and the resulting substrate structures
    1.
    发明授权
    Methods of forming group III-V semiconductor materials on group IV substrates and the resulting substrate structures 有权
    在IV族基底上形成III-V族半导体材料的方法和所得到的衬底结构

    公开(公告)号：US09275861B2

    公开(公告)日：2016-03-01

    申请号：US13927685

    申请日：2013-06-26

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Li Yang ,  Kejia Wang ,  Ashish Baraskar ,  Bin Yang ,  Shurong Liang

    IPC: H01L21/02 ,  H01L29/04 ,  H01L29/20

    CPC classification number: H01L21/02658 ,  H01L21/02373 ,  H01L21/0243 ,  H01L21/02538 ,  H01L29/045 ,  H01L29/20

    Abstract: One method disclosed herein includes forming a patterned mask layer above a surface of a semiconductor substrate, performing at least one etching process through the patterned mask layer to define a plurality of intersecting ridges that define a ridged surface in the substrate, and forming a Group III-V material on the ridged surface of the substrate. An illustrative device disclosed herein includes a Group IV substrate having a ridged surface comprised of a plurality of intersecting ridges and a Group III-V material layer positioned on the ridged surface of the Group IV substrate.

    Abstract translation: 本文公开的一种方法包括在半导体衬底的表面上形成图案化掩模层，通过图案化掩模层执行至少一个蚀刻工艺，以限定在衬底中限定脊状表面的多个相交脊，并形成第III组 -V在基板的脊状表面上的材料。 本文公开的说明性装置包括具有由多个相交脊组成的脊状表面的第IV族衬底和位于第IV族衬底的脊状表面上的III-V族材料层。

    METHODS FOR DEPOSITING AN ALUMINUM OXIDE LAYER OVER GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITS
    2.
    发明申请
    METHODS FOR DEPOSITING AN ALUMINUM OXIDE LAYER OVER GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITS 审中-公开
    用于在整体电路制造中沉积锗永磁体的氧化铝层的方法

    公开(公告)号：US20150093914A1

    公开(公告)日：2015-04-02

    申请号：US14044514

    申请日：2013-10-02

    Applicant: Intermolecular ,  GLOBALFOUNDRIES, Inc.

    Inventor： Bin Yang ,  Abhijit Pethe ,  Albert Lee ,  Amol Joshi ,  Ashish Bodke ,  Kevin Kashefi ,  Salil Mujumdar

    IPC: H01L21/02

    CPC classification number: H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/2807 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate comprising a GeOx layer formed thereon and exposing the semiconductor substrate to first and second atomic layer deposition (ALD) processes. The first ALD process includes exposing the semiconductor substrate to a first gaseous precursor comprising aluminum and exposing the semiconductor substrate to a second gaseous precursor comprising a first oxygen-containing precursor. The second ALD process includes exposing the semiconductor substrate to a first gaseous precursor comprising aluminum and exposing the semiconductor substrate to a second gaseous precursor comprising a second oxygen-containing precursor.

    Abstract translation: 在各种示例性实施例中提供了用于制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供包括形成在其上的GeO x层的锗基半导体衬底，并将半导体衬底暴露于第一和第二原子层沉积（ALD）工艺。 第一ALD工艺包括将半导体衬底暴露于包含铝的第一气态前体，并将半导体衬底暴露于包含第一含氧前体的第二气态前体。 第二ALD工艺包括将半导体衬底暴露于包含铝的第一气态前体，并将半导体衬底暴露于包含第二含氧前体的第二气态前体。

    METHOD TO CONTROL METAL SEMICONDUCTOR MICRO-STRUCTURE
    4.
    发明申请
    METHOD TO CONTROL METAL SEMICONDUCTOR MICRO-STRUCTURE 有权
    控制金属半导体微结构的方法

    公开(公告)号：US20130267090A1

    公开(公告)日：2013-10-10

    申请号：US13908624

    申请日：2013-06-03

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Christian Lavoie ,  Ahmet S. Ozcan ,  Zhen Zhang ,  Bin Yang

    IPC: H01L21/768

    CPC classification number: H01L21/768 ,  H01L21/28518 ,  H01L23/485 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66575 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.

    Abstract translation: 一种形成金属半导体合金的方法，其包括在半导体衬底的第一深度上形成混合金属半导体区域而没有热扩散。 将混合后的金属半导体区域退火以形成织构化的金属半导体合金。 在纹理金属半导体合金上形成第二金属层。 纹理金属半导体合金上的第二金属层然后退火以形成金属半导体合金接触，其中来自第二金属层的金属元素通过织构化金属半导体合金扩散以提供模板化的金属半导体合金。 模板化金属半导体合金的厚度范围为15nm〜50nm的金属半导体合金的晶粒尺寸大于2×。

    Metal-insulator-semiconductor (MIS) contact with controlled defect density
    5.
    发明申请
    Metal-insulator-semiconductor (MIS) contact with controlled defect density 审中-公开
    金属 - 绝缘体 - 半导体（MIS）接触具有受控的缺陷密度

    公开(公告)号：US20150380309A1

    公开(公告)日：2015-12-31

    申请号：US14315718

    申请日：2014-06-26

    Applicant: Intermolecular Inc. ,  GLOBALFOUNDRIES, Inc.

    Inventor： Salil Mujumdar ,  Amol Joshi ,  Kevin Kashefi ,  Albert Sanghyup Lee ,  Abhijit Pethe ,  Bin Yang

    IPC: H01L21/768 ,  H01L23/535

    CPC classification number: H01L29/517 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/02301 ,  H01L21/02312 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/285 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Metal-insulator-semiconductor (MIS) contacts for germanium and its alloys include insulator layers of oxygen-deficient metal oxide deposited by atomic layer deposition (ALD). The oxygen deficiency reduces the tunnel barrier resistance of the insulator layer while maintaining the layer's ability to prevent Fermi-level pinning at the metal/semiconductor interface. The oxygen deficiency is controlled by optimizing one or more ALD parameters such as shortened oxidant pulses, use of less-reactive oxidants such as water, heating the substrate during deposition, TMA “cleaning” of native oxide before deposition, and annealing after deposition. Secondary factors include reduced process-chamber pressure, cooled oxidant, and shortened pulses of the metal precursor.

    Abstract translation: 用于锗及其合金的金属 - 绝缘体 - 半导体（MIS）触点包括通过原子层沉积（ALD）沉积的缺氧金属氧化物的绝缘体层。 缺氧会降低绝缘体层的隧道势垒阻力，同时保持层在金属/半导体界面处防止费米能级钉扎的能力。 通过优化一个或多个ALD参数，例如缩短的氧化剂脉冲，使用较少反应性的氧化剂例如水，在沉积期间加热衬底，在沉积之前对自然氧化物进行TMA“清洁”，以及沉积后的退火来优化一个或多个ALD参数来控制氧缺乏。 次要因素包括降低的处理室压力，冷却的氧化剂和金属前体的缩短的脉冲。

    Method to control metal semiconductor micro-structure
    7.
    发明授权
    Method to control metal semiconductor micro-structure 有权
    控制金属半导体微结构的方法

    公开(公告)号：US08987135B2

    公开(公告)日：2015-03-24

    申请号：US13908624

    申请日：2013-06-03

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Christian Lavoie ,  Ahmet S. Ozcan ,  Zhen Zhang ,  Bin Yang

    IPC: H01L21/44 ,  H01L21/768 ,  H01L21/285 ,  H01L23/485 ,  H01L29/45 ,  H01L29/66

    CPC classification number: H01L21/768 ,  H01L21/28518 ,  H01L23/485 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66575 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.

    Abstract translation: 一种形成金属半导体合金的方法，其包括在半导体衬底的第一深度上形成混合金属半导体区域而没有热扩散。 将混合后的金属半导体区域退火以形成织构化的金属半导体合金。 在纹理金属半导体合金上形成第二金属层。 纹理金属半导体合金上的第二金属层然后退火以形成金属半导体合金接触，其中来自第二金属层的金属元素通过织构化金属半导体合金扩散以提供模板化的金属半导体合金。 模板化金属半导体合金的厚度范围为15nm〜50nm的金属半导体合金的晶粒尺寸大于2×。

    SHORT CHANNEL SEMICONDUCTOR DEVICES WITH REDUCED HALO DIFFUSION
    8.
    发明申请
    SHORT CHANNEL SEMICONDUCTOR DEVICES WITH REDUCED HALO DIFFUSION 审中-公开
    具有减少HALO扩散的短路通道半导体器件

    公开(公告)号：US20130249000A1

    公开(公告)日：2013-09-26

    申请号：US13898033

    申请日：2013-05-20

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Bin Yang ,  Man Fai Ng

    IPC: H01L29/78 ,  H01L27/092

    CPC classification number: H01L29/7816 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833

    Abstract: A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions in the substrate, forming halo regions under the source/drain extension regions, after forming the source drain regions, and forming a gate electrode on the substrate between the source/drain regions. By forming the halo regions after the high temperature processing involved informing the source/drain and source/drain extension regions, halo diffusion is minimized, thereby maintaining sufficient distance between halo regions and reducing short channel NMOS Vt roll-off.

    Abstract translation: 短沟道半导体器件形成有与栅电极的底部彼此分离的晕圈。 实施例包括在形成源极/漏极区域和源极/漏极延伸区域之后注入晕圈。 一个实施例包括在衬底中形成源极/漏极延伸区域，在衬底中形成源极/漏极区域，在形成源极漏极区域之后在源极/漏极延伸区域下方形成卤素区域，以及在衬底上形成栅极电极 源/漏区。 通过在涉及源极/漏极和源极/漏极延伸区域的高温处理之后形成晕圈区域，使得光晕扩散最小化，从而在晕圈区域之间保持足够的距离并且减少短沟道NMOS Vt滚降。

    SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATION METHODS
    9.
    发明申请
    SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATION METHODS 有权
    具有压力区域的半导体器件及相关制造方法

    公开(公告)号：US20130153927A1

    公开(公告)日：2013-06-20

    申请号：US13765474

    申请日：2013-02-12

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Bin Yang ,  Man Fai NG

    IPC: H01L29/78

    CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

    Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a gate structure overlying a region of semiconductor material, wherein the width of the gate structure is aligned with a crystal direction of the semiconductor material. The method continues by forming recesses about the gate structure and forming a stress-inducing semiconductor material in the recesses.

    Abstract translation: 提供了半导体器件结构和相关制造方法的装置。 制造半导体器件结构的一种方法包括形成覆盖半导体材料区域的栅极结构，其中栅极结构的宽度与半导体材料的<100>晶体方向对齐。 该方法通过在栅极结构周围形成凹槽并在凹部中形成应力诱导半导体材料来继续。

    Semiconductor devices having stressor regions and related fabrication methods
    10.
    发明授权
    Semiconductor devices having stressor regions and related fabrication methods 有权
    具有应力区域和相关制造方法的半导体器件

    公开(公告)号：US08674438B2

    公开(公告)日：2014-03-18

    申请号：US13765474

    申请日：2013-02-12

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Bin Yang ,  Man Fai Ng

    IPC: H01L29/04

    CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

    Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a gate structure overlying a region of semiconductor material, wherein the width of the gate structure is aligned with a crystal direction of the semiconductor material. The method continues by forming recesses about the gate structure and forming a stress-inducing semiconductor material in the recesses.

    Abstract translation: 提供了半导体器件结构和相关制造方法的装置。 制造半导体器件结构的一种方法包括形成覆盖半导体材料区域的栅极结构，其中栅极结构的宽度与半导体材料的<100>晶体方向对齐。 该方法通过在栅极结构周围形成凹槽并在凹部中形成应力诱导半导体材料来继续。

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