公开(公告)号：US09405468B2

公开(公告)日：2016-08-02

申请号：US14276025

申请日：2014-05-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Venkatraghavan Bringivijayaraghavan ,  Saurabh Chadha ,  Abhijit Saurabh ,  Saravanan Sethuraman ,  Kenneth L. Wright

IPC: G06F3/00 ,  G06F3/06 ,  G11C5/14 ,  G11C5/06 ,  G06F11/16 ,  G06F11/07 ,  G06F11/30 ,  G06F13/40 ,  G06F13/16 ,  G06F13/28 ,  G06F11/20

CPC classification number: G06F3/06 ,  G06F3/0617 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/0727 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2017 ,  G06F11/2092 ,  G06F11/3027 ,  G06F11/3034 ,  G06F13/1684 ,  G06F13/287 ,  G06F13/4068 ,  G11C5/06 ,  G11C5/148 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.

Abstract translation: 用于存储器设备控制的系统可以包括堆叠的存储器设备和存储器控制器。 堆叠的存储器件可以包括通过电互连连接到封装衬底的芯片堆叠。 堆叠可以包括多个存储器芯片，主控制芯片和次级控制芯片。 主控制芯片和次控制芯片可以通过内部数据总线电连接到多个存储器芯片。 主控制芯片可以具有在内部数据总线和第一外部数据总线之间提供接口的逻辑。 辅助控制芯片可以具有在内部数据总线和第二外部数据总线之间提供接口的逻辑。

公开(公告)号：US09400602B2

公开(公告)日：2016-07-26

申请号：US14464090

申请日：2014-08-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Venkatraghavan Bringivijayaraghavan ,  Saurabh Chadha ,  Abhijit Saurabh ,  Saravanan Sethuraman ,  Kenneth L. Wright

IPC: G06F3/00 ,  G06F3/06 ,  G11C5/14 ,  G11C5/06 ,  G06F11/16 ,  G06F11/07 ,  G06F11/30 ,  G06F13/40 ,  G06F13/16 ,  G06F13/28 ,  G06F11/20

CPC classification number: G06F3/06 ,  G06F3/0617 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/0727 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2017 ,  G06F11/2092 ,  G06F11/3027 ,  G06F11/3034 ,  G06F13/1684 ,  G06F13/287 ,  G06F13/4068 ,  G11C5/06 ,  G11C5/148 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.