公开(公告)号：US10068978B2

公开(公告)日：2018-09-04

申请号：US15472924

申请日：2017-03-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kwan-Yong Lim ,  Christopher Michael Prindle

IPC: H01L29/06 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  G06F17/50 ,  H01L29/45 ,  H01L29/78 ,  H01L29/165

Abstract: At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins. A portion of the lateral over-growth of epitaxial layer on the outer walls of the first and second outer fins is suppressed by the spacer nitride material.

公开(公告)号：US20170200797A1

公开(公告)日：2017-07-13

申请号：US15472924

申请日：2017-03-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kwan-Yong Lim ,  Christopher Michael Prindle

IPC: H01L29/417 ,  H01L29/06 ,  G06F17/50 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L29/41791 ,  G06F17/5072 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/165 ,  H01L29/45 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins. A portion of the lateral over-growth of epitaxial layer on the outer walls of the first and second outer fins is suppressed by the spacer nitride material.

公开(公告)号：US09640533B2

公开(公告)日：2017-05-02

申请号：US14656412

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Christopher Michael Prindle

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/165

CPC classification number: H01L29/41791 ,  G06F17/5072 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/165 ,  H01L29/45 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins. A portion of the lateral over-growth of epitaxial layer on the outer walls of the first and second outer fins is suppressed by the spacer nitride material.

公开(公告)号：US20160268257A1

公开(公告)日：2016-09-15

申请号：US14656412

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Christopher Michael Prindle

IPC: H01L27/088 ,  H01L29/24 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/41791 ,  G06F17/5072 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/165 ,  H01L29/45 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins. A portion of the lateral over-growth of epitaxial layer on the outer walls of the first and second outer fins is suppressed by the spacer nitride material.

Abstract translation: 本文公开的至少一种方法，装置和系统，用于抑制在鳍状场效应晶体管（finFET）的鳍片上形成的外延层的过度生长，以防止单独finFET器件的鳍片之间的短路。 形成第一晶体管的一组翅片。 翅片组包括第一外翅片，内翅片和第二外翅片。 执行氧化物沉积工艺以在该组翅片上沉积氧化物材料。 执行第一凹陷处理以去除一部分氧化物材料。 这使得留在第一和第二外鳍的内壁上的氧化物材料的一部分留下。 进行间隔氮化物沉积工艺。 执行间隔氮化物去除工艺，在第一和第二外部散热片的外壁处留下间隔氮化物材料。 执行第二凹陷处理以从第一和第二外鳍的内壁去除氧化物材料。 在该组翅片上进行外延层沉积。 在第一和第二外部翅片的外壁上的外延层的横向过度生长的一部分被间隔氮化物材料抑制。

公开(公告)号：US09230802B2

公开(公告)日：2016-01-05

申请号：US14282094

申请日：2014-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Neeraj Tripathi ,  Christopher Michael Prindle

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L21/02494 ,  H01L21/02658 ,  H01L29/0847 ,  H01L29/66636 ,  H01L29/78

Abstract: Field-effect transistors (FETs) and methods of fabricating field-effect transistors are provided, with one or both of a source cavity or a drain cavity having different channel junction characteristics. The methods include, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of the transistor, the recessing defining a bottom channel interface surface and a sidewall channel interface surface within the cavity; providing a protective liner over the sidewall channel interface surface, with the bottom channel interface surface being exposed within the cavity; processing the bottom channel interface surface to facilitate forming a first channel junction of the transistor; and removing the protective liner from over the sidewall channel interface surface, and subsequently processing the sidewall channel interface surface to form a second channel junction of the transistor, where the first and second channel junctions have different channel junction characteristics.

Abstract translation: 提供场效应晶体管（FET）和制造场效应晶体管的方法，其中源腔或漏腔中的一个或两个具有不同的沟道结特征。 所述方法包括例如使半导体材料凹陷以形成与晶体管的沟道区相邻的空腔，所述凹陷限定所述空腔内的底部沟道界面表面和侧壁通道界面表面; 在所述侧壁通道界面表面上提供保护衬垫，所述底部通道界面表面暴露在所述空腔内; 处理底部通道界面以便于形成晶体管的第一通道结; 以及从所述侧壁通道界面表面上移除所述保护性衬垫，以及随后处理所述侧壁通道界面以形成所述晶体管的第二通道结，其中所述第一和第二通道结具有不同的通道结特性。