公开(公告)号：US20170242952A1

公开(公告)日：2017-08-24

申请号：US15048066

申请日：2016-02-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haraprasad Nanjundappa ,  Basanth Jagannathan ,  Laura S. Chadwick ,  Dureseti Chidambarrao ,  Christopher V. Baiocco

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Various embodiments include approaches for analyzing integrated circuit (IC) designs. In some cases, an approach includes: defining extraction parameters for the design of the IC for each of a set of failure modes; testing the design of the IC for a failure mode in the set of failure modes; identifying a defined extraction parameter from the design of the IC for at least one of the set of failure modes; correlating the identified defined extracted parameter and each of the at least one failure mode for the design of the IC; and creating a normalized parameter equation representing the correlation of the identified defined extraction parameter with the at least one failure mode for the design of the IC in numerical form.

公开(公告)号：US09431289B2

公开(公告)日：2016-08-30

申请号：US14741618

申请日：2015-06-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Christopher V. Baiocco ,  Michael P. Chudzik ,  Deleep R. Nair ,  Jay M. Shah

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/762 ,  H01L29/0649 ,  H01L29/66537 ,  H01L29/783

Abstract: Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials.

公开(公告)号：US09754071B1

公开(公告)日：2017-09-05

申请号：US15048066

申请日：2016-02-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haraprasad Nanjundappa ,  Basanth Jagannathan ,  Laura S. Chadwick ,  Dureseti Chidambarrao ,  Christopher V. Baiocco

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Various embodiments include approaches for analyzing integrated circuit (IC) designs. In some cases, an approach includes: defining extraction parameters for the design of the IC for each of a set of failure modes; testing the design of the IC for a failure mode in the set of failure modes; identifying a defined extraction parameter from the design of the IC for at least one of the set of failure modes; correlating the identified defined extracted parameter and each of the at least one failure mode for the design of the IC; and creating a normalized parameter equation representing the correlation of the identified defined extraction parameter with the at least one failure mode for the design of the IC in numerical form.