公开(公告)号：US20190074364A1

公开(公告)日：2019-03-07

申请号：US15693537

申请日：2017-09-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Laura J. Schutz ,  Anthony K. Stamper ,  Siva P. Adusumilli ,  Joshua F. Dillon

IPC: H01L29/49 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/3205 ,  H01L29/66

CPC classification number: H01L29/4991 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/32053 ,  H01L21/76224 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/41758 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575

Abstract: A method may include forming a transistor on a substrate, the transistor including a gate, and forming a sacrificial spacer extending along an entirety of a thickness of the gate. A via layer is then formed over/about the gate. The sacrificial spacer is at least partially removed, leaving an air vent opening. An airgap spacer is formed in the dielectric layer by depositing another dielectric layer to close off the air vent opening. The airgap spacer is coincident with at least one sidewall of the gate and extends along an entirety of a thickness of the gate. Gate airgaps may also be provided over the gate. Other embodiments extend the gate and airgap spacer the full thickness of the dielectric layer thereabout. Other embodiments extend the airgap spacer over the gate.

公开(公告)号：US10411107B2

公开(公告)日：2019-09-10

申请号：US15693537

申请日：2017-09-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Laura J. Schutz ,  Anthony K. Stamper ,  Siva P. Adusumilli ,  Joshua F. Dillon

IPC: H01L29/49 ,  H01L29/417 ,  H01L29/423 ,  H01L21/3205 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L21/28

Abstract: A method may include forming a transistor on a substrate, the transistor including a gate, and forming a sacrificial spacer extending along an entirety of a thickness of the gate. A via layer is then formed over/about the gate. The sacrificial spacer is at least partially removed, leaving an air vent opening. An airgap spacer is formed in the dielectric layer by depositing another dielectric layer to close off the air vent opening. The airgap spacer is coincident with at least one sidewall of the gate and extends along an entirety of a thickness of the gate. Gate airgaps may also be provided over the gate. Other embodiments extend the gate and airgap spacer the full thickness of the dielectric layer thereabout. Other embodiments extend the airgap spacer over the gate.