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公开(公告)号:US11915976B2
公开(公告)日:2024-02-27
申请号:US17809109
申请日:2022-06-27
发明人: Li-Wei Chu , Ying-Chi Su , Yu-Kai Chen , Wei-Yip Loh , Hung-Hsu Chen , Chih-Wei Chang , Ming-Hsing Tsai
IPC分类号: H01L21/768 , H01L21/02 , H01L21/3205
CPC分类号: H01L21/76897 , H01L21/02068 , H01L21/02123 , H01L21/32053
摘要: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.
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公开(公告)号:US11887855B2
公开(公告)日:2024-01-30
申请号:US17223506
申请日:2021-04-06
发明人: Xinyu Fu , Srinivas Gandikota , Avgerinos V. Gelatos , Atif Noori , Mei Chang , David Thompson , Steve G. Ghanayem
IPC分类号: H01L21/285 , H01L21/768 , C23C16/14 , C23C16/455 , H01L21/28 , C23C16/06 , H01L21/3205 , C23C16/02 , C23C16/34 , C23C16/42
CPC分类号: H01L21/28562 , C23C16/0272 , C23C16/06 , C23C16/14 , C23C16/345 , C23C16/42 , C23C16/4557 , C23C16/45525 , C23C16/45551 , C23C16/45553 , C23C16/45563 , C23C16/45565 , C23C16/45574 , H01L21/28088 , H01L21/28506 , H01L21/32051 , H01L21/32053 , H01L21/76877
摘要: Provided are atomic layer deposition methods to deposit a tungsten film or tungsten-containing film using a tungsten-containing reactive gas comprising one or more of tungsten pentachloride, a compound with the empirical formula WCl5 or WCl6.
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公开(公告)号:US20190221571A1
公开(公告)日:2019-07-18
申请号:US15885729
申请日:2018-01-31
发明人: Wei-Hsin Liu , Cheng-Hsu Huang , Jui-Min Lee , Yi-Wei Chen
IPC分类号: H01L27/108 , H01L23/532 , H01L23/528 , H01L21/3205 , H01L21/768 , H01L21/285
CPC分类号: H01L27/10894 , H01L21/28556 , H01L21/32053 , H01L21/32055 , H01L21/7685 , H01L21/76856 , H01L21/76864 , H01L21/76879 , H01L23/528 , H01L23/53266 , H01L23/53271 , H01L23/5329 , H01L27/10823 , H01L27/10885 , H01L27/10888 , H01L27/10897
摘要: A semiconductor memory device includes a semiconductor substrate and a patterned conductive structure. The patterned conductive structure is disposed on the semiconductor substrate. The patterned conductive structure includes a first silicon conductive layer, a second silicon conductive layer, an interface layer, a barrier layer, and a metal conductive layer. The second silicon conductive layer is disposed on the first silicon conductive layer. The interface layer is disposed between the first silicon conductive layer and the second silicon conductive layer, and the interface layer includes oxygen. The barrier layer is disposed on the second silicon conductive layer. The metal conductive layer is disposed on the barrier layer.
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公开(公告)号:US20190206732A1
公开(公告)日:2019-07-04
申请号:US15857964
申请日:2017-12-29
发明人: Wei-Min CHEN , Cheng-Wei LIN , Shou-Wei HUANG
IPC分类号: H01L21/768 , H01L27/11568 , H01L27/11582 , H01L23/522 , H01L23/528 , H01L23/532 , H01L23/535 , H01L21/02 , H01L21/3205
CPC分类号: H01L21/76895 , H01L21/02068 , H01L21/32051 , H01L21/32053 , H01L21/32055 , H01L21/76805 , H01L21/76816 , H01L21/76883 , H01L23/5226 , H01L23/5283 , H01L23/53257 , H01L23/53271 , H01L23/535 , H01L27/11568 , H01L27/11582
摘要: A three-dimensional semiconductor device is provided, includes a substrate having an array area and a staircase area; a stack structure having multi-layers formed on the substrate, and the multi-layers comprising conductive layers alternating with insulating layers on the substrate, the stack structure comprising cell-stacks formed on the substrate and disposed in the array area; a conductive channel formed on the substrate and disposed by extending vertically to the multi-layers in the array area; a conductive plug formed on the conductive channel; and a plug contact formed on the conductive plug. The conductive plug includes a polysilicon portion formed on and electrically connected to the conductive channel, and a metal-containing portion formed on the polysilicon portion, wherein the plug contact is electrically connected to the metal-containing portion.
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公开(公告)号:US20190027447A1
公开(公告)日:2019-01-24
申请号:US16036639
申请日:2018-07-16
发明人: Julien DELALLEAU , Christian RIVERO
IPC分类号: H01L23/00 , H01L23/528 , H01L29/06 , H01L27/088 , H01L29/10 , H01L27/02 , H01L21/8234 , H01L21/3205 , H01L21/3213 , H01L29/49 , H01L29/45 , H01L29/08
CPC分类号: H01L23/573 , H01L21/32053 , H01L21/32133 , H01L21/823437 , H01L21/823475 , H01L21/823481 , H01L23/528 , H01L27/0207 , H01L27/088 , H01L29/0649 , H01L29/0847 , H01L29/1079 , H01L29/45 , H01L29/4916
摘要: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.
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公开(公告)号:US20180366328A1
公开(公告)日:2018-12-20
申请号:US15988854
申请日:2018-05-24
发明人: He REN , Minrui YU , Mehul B. NAIK
IPC分类号: H01L21/285 , H01L21/768 , H01L23/532 , H01L21/67
CPC分类号: H01L21/2855 , C23C14/0682 , C23C14/3464 , C23C14/352 , H01J37/3417 , H01J37/3429 , H01J37/3435 , H01J37/3447 , H01L21/32053 , H01L21/67138 , H01L21/76877 , H01L23/53209 , H01L23/53271
摘要: Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a NixSi1-x layer on the substrate, where x is between about 0.01 and about 0.99.
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公开(公告)号:US10083860B2
公开(公告)日:2018-09-25
申请号:US15495901
申请日:2017-04-24
发明人: Chen-Liang Liao , Chia-Yao Liang , Jui-Long Chen , Sheng-Yuan Lin , Yi-Lii Huang , Kuo-Hsi Lee , Po-An Chen
IPC分类号: H01L29/06 , H01L21/768 , H01L21/3205 , H01L21/3213 , H01L29/49
CPC分类号: H01L21/76834 , H01L21/283 , H01L21/28518 , H01L21/32053 , H01L21/32134 , H01L21/32135 , H01L21/32139 , H01L21/823437 , H01L21/823481 , H01L29/0649 , H01L29/42364 , H01L29/4933
摘要: A method of forming a semiconductor structure includes; (i) forming an isolation structure in a semiconductor substrate, the isolation structure electrically isolating device regions of the semiconductor substrate; (ii) forming a gate structure extending from one of the device regions to the isolation structure; (iii) forming a resist protective oxide layer overlaying the gate structure and the isolation structure; and (iv) patterning the resist protective oxide layer to form a patterned resist protective oxide that covers at least a portion of the isolation structure and a portion of the gate structure on the isolation structure.
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公开(公告)号:US10043885B2
公开(公告)日:2018-08-07
申请号:US15899070
申请日:2018-02-19
发明人: Sheng-Hsuan Lin , Chih-Wei Chang
IPC分类号: H01L21/00 , H01L29/66 , H01L21/285 , H01L21/3205 , H01L21/477 , H01L21/768 , H01L29/417
CPC分类号: H01L29/665 , H01L21/28518 , H01L21/32053 , H01L21/477 , H01L21/76805 , H01L21/76843 , H01L21/7685 , H01L21/76855 , H01L21/76897 , H01L29/41791 , H01L29/66795
摘要: A method includes performing a first sputtering to form a first metal film on a surface of a semiconductor region. The first sputtering is performed using a first ion energy. The method further includes performing a second sputtering to form a second metal film over and contacting the first metal film, wherein the first and the second metal films includes a same metal. The second sputtering is performed using a second ion energy lower than the first ion energy. An annealing is performed to react the first and the second metal films with the semiconductor region to form a metal silicide.
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公开(公告)号:US20180190753A1
公开(公告)日:2018-07-05
申请号:US15419002
申请日:2017-01-30
IPC分类号: H01L49/02 , H01L21/3205 , H01L21/027
CPC分类号: H01L28/20 , H01L21/0273 , H01L21/32053 , H01L21/32055 , H01L28/24
摘要: Disclosed examples include a resistor comprising a semiconductor structure having a length dimension with first and second ends spaced from one another and an intermediate region between the first and second ends, first and second metal-semiconductor compound structures on the semiconductor structure proximate the first and second ends of the semiconductor structure, the first and second metal-semiconductor compound structures being spaced apart from each other along the length dimension of the semiconductor structure, and at least one intermediate metal-semiconductor compound structure on a portion of the intermediate region of the semiconductor structure between the first and second ends, the intermediate metal-semiconductor compound structure being spaced apart from the first and second metal-semiconductor compound structures on the semiconductor structure.
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公开(公告)号:US09887269B2
公开(公告)日:2018-02-06
申请号:US14954823
申请日:2015-11-30
发明人: Kuo-Cheng Ching , Ching-Fang Huang , Carlos H. Diaz , Chih-Hao Wang , Wen-Hsing Hsieh , Ying-Keung Leung
IPC分类号: H01L29/423 , H01L29/06 , H01L29/417 , H01L29/78 , H01L21/3205 , H01L21/84
CPC分类号: H01L29/42392 , H01L21/32053 , H01L21/845 , H01L29/0673 , H01L29/41791 , H01L29/665 , H01L29/66545 , H01L29/785
摘要: A semiconductor device includes a source/drain feature disposed over a substrate. The source/drain feature includes a first nanowire, a second nanowire disposed over the first nanowire, a cladding layer disposed over the first nanowire and the second nanowire and a spacer layer extending from the first nanowire to the second nanowire. The device also includes a conductive feature disposed directly on the source/drain feature such that the conductive feature physically contacts the cladding layer and the spacer layer.
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