公开(公告)号：US08856715B1

公开(公告)日：2014-10-07

申请号：US13948249

申请日：2013-07-23

Applicant: GlobalFoundries Inc.

Inventor： Jason Stephens ,  Vikrant Chauhan ,  Lawrence Clevenger ,  Ning Lu ,  Albert Chu

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: Methodologies enabling BEoL VNCAPs in ICs and resulting devices are disclosed. Embodiments include: providing a plurality of mandrel recesses extending horizontally on a substrate, each of the mandrel recesses having an identical width and being separated from another one of the mandrel recesses by an identical distance; providing a plurality of routes, each of the plurality of routes being positioned in a different one of the mandrel recesses; and providing first and second vertical segments on the substrate, the first vertical segment being connected to a set of the plurality of routes and separated from the second vertical segment, and the second vertical segment being separated from the set of routes.

Abstract translation: 公开了在IC和结果设备中使用BEoL VNCAP的方法。 实施例包括：提供在基板上水平延伸的多个心轴凹槽，每个心轴凹槽具有相同的宽度，并且与另一个心轴凹槽分开相同的距离; 提供多条路线，所述多条路线中的每条路线被定位在不同的心轴凹槽中; 以及在所述基板上提供第一和第二垂直段，所述第一垂直段连接到所述多条路线的一组，并与所述第二垂直段分离，并且所述第二垂直段与所述路线组分离。

公开(公告)号：US10031989B2

公开(公告)日：2018-07-24

申请号：US14546065

申请日：2014-11-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ralph M. Alfano ,  Arnold E. Baizley ,  Ning Lu ,  Judith H. McCullen ,  Cole E. Zemke

IPC: G06F17/50

Abstract: Disclosed are a system and a method for integrated circuit (IC) performance modeling, wherein a design layout of an IC is analyzed to identify a first conductive shape (e.g., an internal local interconnect or contact bar shape) on a diffusion boundary shape of a semiconductor device and to also identify the first conductive shape's connectivity to any second conductive shapes (e.g., a via, via bar, or external local interconnect shapes) inside and/or outside the limits of the diffusion boundary shape. A condensed resistance model for the first conductive shape is selected from a model library based on the previously identified connectivity. The selected condensed resistance model will have a lesser number of nodes and/or resistive elements than a full resistance model for the conductive shape. The selected condensed resistance model is used to construct a condensed netlist, which is used in a combined netlist to simulate IC performance.