公开(公告)号：US20190148245A1

公开(公告)日：2019-05-16

申请号：US15810557

申请日：2017-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Rick Carter ,  Vikrant Chauhan ,  George Jonathan Kluth ,  Anurag Mittal ,  David Pritchard ,  Mahbub Rashed

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L27/12 ,  H01L29/49

CPC classification number: H01L21/823871 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/41783 ,  H01L29/4941 ,  H01L2924/0002

Abstract: A method of forming contacts includes forming a plurality of transistor devices separated by shallow trench insulator regions, the transistor devices each comprising a semiconductor substrate, a buried insulator layer on the semiconductor bulk substrate, a semiconductor layer on the buried insulator layer, a high-k metal gate stack on the semiconductor layer and a gate electrode above the high-k metal gate stack, raised source/drain regions on the semiconductor layer, and a silicide contact layer above the raised source/drain regions and the gate electrode, providing an interlayer dielectric stack on the silicide contact layer and planarizing the interlayer dielectric stack, patterning a plurality of contacts through the interlayer dielectric stack onto the raised source/drain regions, and, for at least some of the contacts, patterning laterally extended contact regions above the contacts, the laterally extended contact regions extending over shallow trench insulator regions neighboring the corresponding raised source/drain regions.

公开(公告)号：US10199270B2

公开(公告)日：2019-02-05

申请号：US15605327

申请日：2017-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Colin Bombardier ,  Ming He ,  Vikrant Chauhan ,  Anbu Selvam KM Mahalingam ,  Keith Donegan

IPC: H01L21/768 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528

Abstract: Interconnect structures and methods of fabricating an interconnect structure. First and second non-mandrel interconnects are formed in an interlayer dielectric layer. The first non-mandrel interconnect and the second non-mandrel interconnect have respective side surfaces that extend in a first direction. The connector interconnect extends in a second direction transverse to the first direction from the side surface of the first non-mandrel interconnect to the side surface of the second non-mandrel interconnect.

公开(公告)号：US20180342421A1

公开(公告)日：2018-11-29

申请号：US15605327

申请日：2017-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Colin Bombardier ,  Ming He ,  Vikrant Chauhan ,  Anbu Selvam KM Mahalingam ,  Keith Donegan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/66

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L22/32 ,  H01L23/5226 ,  H01L23/528

Abstract: Interconnect structures and methods of fabricating an interconnect structure. First and second non-mandrel interconnects are formed in an interlayer dielectric layer. The first non-mandrel interconnect and the second non-mandrel interconnect have respective side surfaces that extend in a first direction. The connector interconnect extends in a second direction transverse to the first direction from the side surface of the first non-mandrel interconnect to the side surface of the second non-mandrel interconnect.

公开(公告)号：US10796973B2

公开(公告)日：2020-10-06

申请号：US16425387

申请日：2019-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mankyu Yang ,  Vara Govindeswara Reddy Vakada ,  Edward Maciejewski ,  Brian Greene ,  Atsushi Ogino ,  Vikrant Chauhan ,  Prianka Sengupta

IPC: H01L29/423 ,  H01L21/66 ,  G01R31/26 ,  H01L23/528 ,  H01L23/522

Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.

公开(公告)号：US10347543B2

公开(公告)日：2019-07-09

申请号：US15810557

申请日：2017-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Rick Carter ,  Vikrant Chauhan ,  George Jonathan Kluth ,  Anurag Mittal ,  David Pritchard ,  Mahbub Rashed

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L27/12 ,  H01L29/49

Abstract: A method of forming contacts includes forming a plurality of transistor devices separated by shallow trench insulator regions, the transistor devices each comprising a semiconductor substrate, a buried insulator layer on the semiconductor bulk substrate, a semiconductor layer on the buried insulator layer, a high-k metal gate stack on the semiconductor layer and a gate electrode above the high-k metal gate stack, raised source/drain regions on the semiconductor layer, and a silicide contact layer above the raised source/drain regions and the gate electrode, providing an interlayer dielectric stack on the silicide contact layer and planarizing the interlayer dielectric stack, patterning a plurality of contacts through the interlayer dielectric stack onto the raised source/drain regions, and, for at least some of the contacts, patterning laterally extended contact regions above the contacts, the laterally extended contact regions extending over shallow trench insulator regions neighboring the corresponding raised source/drain regions.

公开(公告)号：US10147783B2

公开(公告)日：2018-12-04

申请号：US15463465

申请日：2017-03-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Atsushi Ogino ,  Vikrant Chauhan ,  Kong Boon Yeap ,  Ahmed Hassan

IPC: H01L49/02

Abstract: Structures for an on-chip capacitor and methods of forming an on-chip capacitor. A metal terminal is formed that has a side edge. Metal fingers are formed that have a parallel arrangement. Floating islands comprised of a metal are formed and are electrically isolated from the metal fingers. Each of the metal fingers has an end and extends from the side edge of the metal terminal toward the end. Each of the floating islands is arranged in a spaced relationship with the end of a respective one of the metal fingers.

公开(公告)号：US08856715B1

公开(公告)日：2014-10-07

申请号：US13948249

申请日：2013-07-23

Applicant: GlobalFoundries Inc.

Inventor： Jason Stephens ,  Vikrant Chauhan ,  Lawrence Clevenger ,  Ning Lu ,  Albert Chu

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: Methodologies enabling BEoL VNCAPs in ICs and resulting devices are disclosed. Embodiments include: providing a plurality of mandrel recesses extending horizontally on a substrate, each of the mandrel recesses having an identical width and being separated from another one of the mandrel recesses by an identical distance; providing a plurality of routes, each of the plurality of routes being positioned in a different one of the mandrel recesses; and providing first and second vertical segments on the substrate, the first vertical segment being connected to a set of the plurality of routes and separated from the second vertical segment, and the second vertical segment being separated from the set of routes.

Abstract translation: 公开了在IC和结果设备中使用BEoL VNCAP的方法。 实施例包括：提供在基板上水平延伸的多个心轴凹槽，每个心轴凹槽具有相同的宽度，并且与另一个心轴凹槽分开相同的距离; 提供多条路线，所述多条路线中的每条路线被定位在不同的心轴凹槽中; 以及在所述基板上提供第一和第二垂直段，所述第一垂直段连接到所述多条路线的一组，并与所述第二垂直段分离，并且所述第二垂直段与所述路线组分离。

公开(公告)号：US10790204B2

公开(公告)日：2020-09-29

申请号：US16185696

申请日：2018-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mankyu Yang ,  Vara Govindeswara Reddy Vakada ,  Edward Maciejewski ,  Brian Greene ,  Atsushi Ogino ,  Vikrant Chauhan ,  Prianka Sengupta

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/66 ,  H01L29/772

Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a test pad, a device-under-testing having one or more source/drain regions, and a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines that are connected with the test pad. One or more contacts, which are arranged between the metallization level and the device-under-testing, directly connect the one or more interconnect lines with the one or more source/drain regions.

公开(公告)号：US10311186B2

公开(公告)日：2019-06-04

申请号：US15096551

申请日：2016-04-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jaime Bravo ,  Vikrant Chauhan ,  Piyush Pathak ,  Shobhit Malik ,  Uwe Paul Schroeder

IPC: G06F17/50

Abstract: Methodologies and a device for assessing integrated circuit and pattern for yield risk based on 3D simulation of semiconductor patterns are provided. Embodiments include generating, with a processor, a 3D simulation of semiconductor patterns; obtaining critical dimensions of distances between layers or within a layer of the 3D simulation of semiconductor patterns; comparing the set of critical dimensions with predefined minimum dimensions; and yield scoring each of the semiconductor patterns of the 3D simulation based on the comparing step.

公开(公告)号：US20180040505A1

公开(公告)日：2018-02-08

申请号：US15225994

申请日：2016-08-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sandeep Gaan ,  Shishir Ray ,  Vikrant Chauhan

IPC: H01L21/762 ,  H01L21/324

CPC classification number: H01L21/76283 ,  H01L21/324

Abstract: A method includes forming a trench in a stack comprising a substrate, a buried oxide layer formed above the substrate, a semiconductor layer formed above the buried oxide layer and a hard mask layer formed above the semiconductor layer. A first liner is formed in the trench. A first oxide layer is formed in the trench. A diffusionless anneal process is performed to densify the first oxide layer. The first oxide layer is recessed to define a recess. A second oxide layer is formed in the recess.