公开(公告)号：US08856715B1

公开(公告)日：2014-10-07

申请号：US13948249

申请日：2013-07-23

Applicant: GlobalFoundries Inc.

Inventor： Jason Stephens ,  Vikrant Chauhan ,  Lawrence Clevenger ,  Ning Lu ,  Albert Chu

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: Methodologies enabling BEoL VNCAPs in ICs and resulting devices are disclosed. Embodiments include: providing a plurality of mandrel recesses extending horizontally on a substrate, each of the mandrel recesses having an identical width and being separated from another one of the mandrel recesses by an identical distance; providing a plurality of routes, each of the plurality of routes being positioned in a different one of the mandrel recesses; and providing first and second vertical segments on the substrate, the first vertical segment being connected to a set of the plurality of routes and separated from the second vertical segment, and the second vertical segment being separated from the set of routes.

Abstract translation: 公开了在IC和结果设备中使用BEoL VNCAP的方法。 实施例包括：提供在基板上水平延伸的多个心轴凹槽，每个心轴凹槽具有相同的宽度，并且与另一个心轴凹槽分开相同的距离; 提供多条路线，所述多条路线中的每条路线被定位在不同的心轴凹槽中; 以及在所述基板上提供第一和第二垂直段，所述第一垂直段连接到所述多条路线的一组，并与所述第二垂直段分离，并且所述第二垂直段与所述路线组分离。

公开(公告)号：US10388729B2

公开(公告)日：2019-08-20

申请号：US15155761

申请日：2016-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John Zhang ,  Lawrence Clevenger ,  Kangguo Cheng ,  Balasubramanian Haran

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/165

Abstract: Devices and methods of fabricating integrated circuit devices for forming uniform nano sheet spacers self-aligned to the channel are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, multiple layers disposed on the substrate, and at least one gate structure disposed on the multiple layers; depositing an oxide layer over the device; etching the oxide layer to form replacement sidewall spacers positioned on left and right sides of the at least one gate structure; etching the multiple layers to form at least one stack structure; and forming a plurality of recesses within the at least one stack structure. Also disclosed is an intermediate semiconductor, which includes, for instance: a substrate; and at least one stack structure disposed on the substrate, the at least one stack structure having an upper portion and a base portion, wherein a plurality of recesses are located within the base portion.