公开(公告)号：US10256134B2

公开(公告)日：2019-04-09

申请号：US15618491

申请日：2017-06-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ricardo P. Mikalo ,  Martin Gerhardt

IPC: H01L21/20 ,  H01L21/76 ,  H01L49/02 ,  H01L23/367

Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: a first heat dissipative element disposed between a pair of shallow trench isolations (STIs) in a substrate, and a first polysilicon resistor in a polysilicon layer positioned over the substrate and the pair of STIs, the first polysilicon resistor in thermal communication with the first heat dissipative element. The structure can also include a second polysilicon resistor in the polysilicon layer, the second polysilicon resistor laterally separated from the first polysilicon resistor, and the first heat dissipative element in thermal communication with the first polysilicon resistor and the second polysilicon element. The structure can also include a second heat dissipative element, the second heat dissipative element in a different directional orientation than the first heat dissipative element.

公开(公告)号：US10147659B1

公开(公告)日：2018-12-04

申请号：US15652661

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Uwe Dersch ,  Ricardo P. Mikalo ,  Thomas Merbeth

IPC: H01L21/66

Abstract: Disclosed is a method of manufacturing integrated circuit (IC) chips, which includes forming routing structure(s) that facilitate process limiting yield (PLY) testing of test devices. A routing structure includes an array of link-up regions and a set of metal pads surrounding that array. Each link-up region includes two sections, each having two nodes electrically connected to the terminals of a corresponding two-terminal test device. During PLY testing with a probe card, electrical connections between the test devices and the metal pads through the link-up regions allow each test device to be tested individually. Optionally, additional routing structures with the same footprint are formed down the line and stacked one above the other. These additional routing structures are used for PLY testing with the same probe card. Optionally, dummy pads are formed between stacked routing structures to improve robustness. Also disclosed is a semiconductor structure formed according to this method.

公开(公告)号：US20180358259A1

公开(公告)日：2018-12-13

申请号：US15618491

申请日：2017-06-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ricardo P. Mikalo ,  Martin Gerhardt

IPC: H01L21/76 ,  H01L49/02 ,  H01L23/367

CPC classification number: H01L21/76 ,  H01L23/367 ,  H01L28/20

Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: a first heat dissipative element disposed between a pair of shallow trench isolations (STIs) in a substrate, and a first polysilicon resistor in a polysilicon layer positioned over the substrate and the pair of STIs, the first polysilicon resistor in thermal communication with the first heat dissipative element. The structure can also include a second polysilicon resistor in the polysilicon layer, the second polysilicon resistor laterally separated from the first polysilicon resistor, and the first heat dissipative element in thermal communication with the first polysilicon resistor and the second polysilicon element. The structure can also include a second heat dissipative element, the second heat dissipative element in a different directional orientation than the first heat dissipative element.

公开(公告)号：US09087587B2

公开(公告)日：2015-07-21

申请号：US13834019

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ricardo P. Mikalo ,  Stefan Flachowsky

IPC: G11C11/34 ,  G11C16/04 ,  H01L27/115

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C16/045 ,  H01L27/11558 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4916

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, a second well, formed within the first well, and doped with the first conductivity-determining impurity, and a third well spaced apart from the first and second wells and doped with the second conductivity-determining impurity. The integrated circuit further includes a floating gate structure formed over the semiconductor substrate. The floating gate structure includes a first gate element disposed over the second well and being separated from the second well with a dielectric layer, a second gate element disposed over the third well and being separated from the third well with the dielectric layer, and a conductive connector.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，集成电路包括掺杂有第一导电性确定杂质的半导体衬底。 半导体衬底在其中形成有掺杂有与第一导电率确定杂质不同的第二导电率确定杂质的第一阱，形成在第一阱内的第二阱，并且掺杂有第一导电率确定杂质，以及 第三阱与第一和第二阱间隔开并掺杂有第二导电性确定杂质。 集成电路还包括形成在半导体衬底上的浮栅结构。 浮置栅极结构包括设置在第二阱上并与第二阱分离的第一栅极元件，其具有电介质层，第二栅极元件设置在第三阱上并与第三阱与介电层分离，并且导电 连接器。

公开(公告)号：US20140269060A1

公开(公告)日：2014-09-18

申请号：US13834019

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Ricardo P. Mikalo ,  Stefan Flachowsky

IPC: H01L27/115 ,  G11C16/04

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C16/045 ,  H01L27/11558 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4916

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, a second well, formed within the first well, and doped with the first conductivity-determining impurity, and a third well spaced apart from the first and second wells and doped with the first conductivity-determining impurity. The integrated circuit further includes a floating gate structure formed over the semiconductor substrate. The floating gate structure includes a first gate element disposed over the second well and being separated from the second well with a dielectric layer, a second gate element disposed over the third well and being separated from the third well with the dielectric layer, and a conductive connector.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，集成电路包括掺杂有第一导电性确定杂质的半导体衬底。 半导体衬底在其中形成有掺杂有与第一导电率确定杂质不同的第二导电率确定杂质的第一阱，形成在第一阱内的第二阱，并且掺杂有第一导电率确定杂质，以及 第三阱与第一阱和第二阱间隔开并掺杂有第一导电性确定杂质。 集成电路还包括形成在半导体衬底上的浮栅结构。 浮置栅极结构包括设置在第二阱上并与第二阱分离的第一栅极元件，其具有电介质层，第二栅极元件设置在第三阱上并与第三阱与介电层分离，并且导电 连接器。