公开(公告)号：US09786657B1

公开(公告)日：2017-10-10

申请号：US15089914

申请日：2016-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Uwe Dersch ,  Ricardo Pablo. Mikalo

IPC: H01L27/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/0629 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0883 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207 ,  H01L28/20 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/66166 ,  H01L29/7838 ,  H01L29/8605

Abstract: A semiconductor structure includes a bulk semiconductor substrate, an electrically insulating layer over the substrate, an active layer of semiconductor material over the electrically insulating layer and a transistor. The transistor includes an active region, a gate electrode region and an isolation junction region. The active region is provided in the active layer of semiconductor material and includes a source region, a channel region and a drain region. The gate electrode region is provided in the bulk semiconductor substrate and has a first type of doping. The isolation junction region is formed in the bulk semiconductor substrate and has a second type of doping opposite the first type of doping. The isolation junction region separates the gate electrode region from a portion of the bulk semiconductor substrate other than the gate electrode region that has the first type of doping.

公开(公告)号：US20170067955A1

公开(公告)日：2017-03-09

申请号：US14848804

申请日：2015-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Uwe Dersch ,  Ricardo Pablo. Mikalo

IPC: G01R31/26 ,  G01R31/02 ,  H01L29/417 ,  H01L29/423 ,  H01L27/12 ,  H01L29/08

CPC classification number: G01R31/2621 ,  G01R31/2884 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/42384

Abstract: A semiconductor test structure is provided for detecting raised source/drain regions-gate electrode shorts, including a semiconductor substrate, FETs formed on the semiconductor substrate, raised source/drain regions of the FETs formed on the semiconductor substrate, a gate electrode structure comprising multiple gate electrodes of the FETs arranged in parallel to each other, and a first electrical terminal electrically connected to the gate electrode structure, and wherein no electrical contacts to the raised source/drain regions are present between the multiple gate electrodes of the gate electrode structure.

Abstract translation: 提供半导体测试结构用于检测凸起的源极/漏极区域 - 包括半导体衬底的栅极电极短路，形成在半导体衬底上的FET，形成在半导体衬底上的FET的升高的源极/漏极区域，包括多个 所述FET的栅电极彼此平行地布置，以及电连接到所述栅电极结构的第一电端子，并且其中在所述栅极电极结构的所述多个栅电极之间没有与所述凸起的源极/漏极区的电接触。

公开(公告)号：US09257353B1

公开(公告)日：2016-02-09

申请号：US14523266

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ricardo Pablo Mikalo ,  Uwe Dersch

IPC: H01L27/00 ,  H01L21/66 ,  H01L29/861 ,  H01L27/02 ,  H01L27/06

CPC classification number: H01L22/34 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/0676 ,  H01L29/8613

Abstract: Integrated circuits that include bi-directional protection diode structures are disclosed. In one example, an integrated circuit includes a test circuit portion for testing the functionality of the integrated circuit during or after fabrication of the integrated circuit. The test circuit portion includes first, second, and third diode structures and a resistor structure. The first and third diode structures are in parallel with one another and in series with the resistor, and the resistor and the first and third diode structures are in series with the second diode structure. The first and third diode structures are configured for current flow in a first direction and the second diode structure is configured for current flow in a second direction that is opposite the first direction.

Abstract translation: 公开了包括双向保护二极管结构的集成电路。 在一个示例中，集成电路包括用于在集成电路制造期间或之后测试集成电路的功能的测试电路部分。 测试电路部分包括第一，第二和第三二极管结构和电阻器结构。 第一和第三二极管结构彼此并联并且与电阻器串联，并且电阻器和第一和第三二极管结构与第二二极管结构串联。 第一和第三二极管结构被配置为在第一方向上的电流流动，并且第二二极管结构被配置为在与第一方向相反的第二方向上的电流流动。

公开(公告)号：US10147659B1

公开(公告)日：2018-12-04

申请号：US15652661

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Uwe Dersch ,  Ricardo P. Mikalo ,  Thomas Merbeth

IPC: H01L21/66

Abstract: Disclosed is a method of manufacturing integrated circuit (IC) chips, which includes forming routing structure(s) that facilitate process limiting yield (PLY) testing of test devices. A routing structure includes an array of link-up regions and a set of metal pads surrounding that array. Each link-up region includes two sections, each having two nodes electrically connected to the terminals of a corresponding two-terminal test device. During PLY testing with a probe card, electrical connections between the test devices and the metal pads through the link-up regions allow each test device to be tested individually. Optionally, additional routing structures with the same footprint are formed down the line and stacked one above the other. These additional routing structures are used for PLY testing with the same probe card. Optionally, dummy pads are formed between stacked routing structures to improve robustness. Also disclosed is a semiconductor structure formed according to this method.

公开(公告)号：US10048311B2

公开(公告)日：2018-08-14

申请号：US14848804

申请日：2015-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Uwe Dersch ,  Ricardo Pablo Mikalo

IPC: G01R31/02 ,  G01R31/26 ,  H01L27/12 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  G01R31/28

Abstract: A semiconductor test structure is provided for detecting raised source/drain regions-gate electrode shorts, including a semiconductor substrate, FETs formed on the semiconductor substrate, raised source/drain regions of the FETs formed on the semiconductor substrate, a gate electrode structure comprising multiple gate electrodes of the FETs arranged in parallel to each other, and a first electrical terminal electrically connected to the gate electrode structure, and wherein no electrical contacts to the raised source/drain regions are present between the multiple gate electrodes of the gate electrode structure.

公开(公告)号：US20170287901A1

公开(公告)日：2017-10-05

申请号：US15089914

申请日：2016-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Uwe Dersch ,  Ricardo Pablo. Mikalo

IPC: H01L27/06 ,  H01L21/84 ,  H01L29/08 ,  H01L27/12 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0629 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0883 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207 ,  H01L28/20 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/66166 ,  H01L29/7838 ,  H01L29/8605

Abstract: A semiconductor structure includes a bulk semiconductor substrate, an electrically insulating layer over the substrate, an active layer of semiconductor material over the electrically insulating layer and a transistor. The transistor includes an active region, a gate electrode region and an isolation junction region. The active region is provided in the active layer of semiconductor material and includes a source region, a channel region and a drain region. The gate electrode region is provided in the bulk semiconductor substrate and has a first type of doping. The isolation junction region is formed in the bulk semiconductor substrate and has a second type of doping opposite the first type of doping. The isolation junction region separates the gate electrode region from a portion of the bulk semiconductor substrate other than the gate electrode region that has the first type of doping.