INTEGRATED CIRCUIT DECOUPLING CAPACITOR ARRANGEMENT
    1.
    发明申请
    INTEGRATED CIRCUIT DECOUPLING CAPACITOR ARRANGEMENT 审中-公开
    集成电路解耦电容器布置

    公开(公告)号:US20140110772A1

    公开(公告)日:2014-04-24

    申请号:US14075517

    申请日:2013-11-08

    CPC classification number: H01L27/06 H01L27/0629 H01L27/0805

    Abstract: A decoupling capacitor arrangement is provided for an integrated circuit. The apparatus includes a plurality of decoupling capacitor arrays electrically connected in parallel with one another. Each of the arrays includes a plurality of decoupling capacitors and a current limiting element. The decoupling capacitors of each array are electrically connected in parallel with one another. The current limiting element is connected in series with the plurality of decoupling capacitors.

    Abstract translation: 为集成电路提供去耦电容器布置。 该装置包括彼此并联电连接的多个去耦电容器阵列。 每个阵列包括多个去耦电容器和限流元件。 每个阵列的去耦电容彼此并联电连接。 限流元件与多个去耦电容器串联连接。

    Assessment of HCI in logic circuits based on AC stress in discrete FETs

    公开(公告)号:US10126354B1

    公开(公告)日:2018-11-13

    申请号:US15635711

    申请日:2017-06-28

    Abstract: CMOS switching devices are connected to testing equipment that applies AC to stress the CMOS switching devices. The testing equipment varies rise and fall times of drain and gate voltages, and varies offsets of the drain and gate voltages of the CMOS switching devices. The amount of hot carrier injection (HCI) within the CMOS switching devices is measured when the rise and fall times of the drain and gate voltages cross over, to establish AC HCI contribution to device degradation of the CMOS switching devices. Further, these methods can correlate the AC HCI contribution of the CMOS switching devices to CMOS logic devices based on ring oscillator (RO) degradation of ROs similarly tested or simulated, to produce AC HCI contribution for the CMOS logic devices.

Patent Agency Ranking