公开(公告)号：US10199463B2

公开(公告)日：2019-02-05

申请号：US15906355

申请日：2018-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Waikin Li ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L29/06 ,  H01L29/423 ,  H01L27/108 ,  H01L23/522 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775 ,  H01L49/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator. At least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith; and at least one wordline formed on vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material.

公开(公告)号：US09966431B2

公开(公告)日：2018-05-08

申请号：US15078112

申请日：2016-03-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Waikin Li ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L29/06 ,  H01L27/108 ,  H01L29/423 ,  H01L23/522

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  H01L23/5226 ,  H01L27/10805 ,  H01L28/00 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator. At least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith; and at least one wordline formed on vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material.