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    Nanowire-based vertical memory cell array having a metal layer interposed between a common back plate and the nanowires
    1.
    发明授权
    Nanowire-based vertical memory cell array having a metal layer interposed between a common back plate and the nanowires 有权

    公开(公告)号：US10199463B2

    公开(公告)日：2019-02-05

    申请号：US15906355

    申请日：2018-02-27

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Waikin Li ,  Chengwen Pei ,  Ping-Chuan Wang

    IPC: H01L29/06 ,  H01L29/423 ,  H01L27/108 ,  H01L23/522 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775 ,  H01L49/02

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator. At least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith; and at least one wordline formed on vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material.

    Inline measurement of through-silicon via depth
    5.
    发明授权
    Inline measurement of through-silicon via depth 有权

    公开(公告)号：US09865514B2

    公开(公告)日：2018-01-09

    申请号：US14643436

    申请日：2015-03-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hanyi Ding ,  J. Edwin Hostetter ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC: H01L21/66 ,  H01L21/304

    CPC classification number: H01L22/26 ,  H01L21/304 ,  H01L22/14 ,  H01L22/34

    Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.

    Commonly-bodied field-effect transistors
    6.
    发明授权
    Commonly-bodied field-effect transistors 有权

    公开(公告)号：US09818652B1

    公开(公告)日：2017-11-14

    申请号：US15140025

    申请日：2016-04-27

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Chengwen Pei ,  Ping-Chuan Wang ,  Kai D. Feng

    IPC: H01L27/12 ,  H01L21/84 ,  H01L21/3065 ,  H01L21/28

    CPC classification number: H01L21/84 ,  H01L27/1203

    Abstract: Structures for a commonly-bodied field-effect transistors and methods of forming such structures. The structure includes a body of semiconductor material defined by a trench isolation region in a semiconductor substrate. The body includes a plurality of first sections, a plurality of second sections, and a third section, the second sections coupling the first sections and the third section. The third section includes a contact region used as a common-body contact for at least the first sections. The first sections and the third section have a first height and the second sections have a second height that is less than the first height.

    Precision trench capacitor
    8.
    发明授权
    Precision trench capacitor 有权
    精密沟槽电容器

    公开(公告)号：US09240406B2

    公开(公告)日：2016-01-19

    申请号：US14257143

    申请日：2014-04-21

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Kai D. Feng ,  Dan Moy ,  Chengwen Pei ,  Robert R. Robison ,  Pinping Sun ,  Richard A. Wachnik ,  Ping-Chuan Wang

    IPC: H01L27/07 ,  H01L29/66 ,  H01L29/94

    CPC classification number: H01L27/0733 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/11206 ,  H01L29/66181 ,  H01L29/945

    Abstract: A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.

    Abstract translation: 电容器结构可以包括多个沟槽电容器的并联连接。 电连接多个沟槽电容器的第一节点以提供电容器结构的第一节点。 多个沟槽电容器的第二节点通过电容器结构的第二节点处的至少一个可编程电连接电连接在一起。 每个可编程电气连接可以包括可编程电熔丝和场效应晶体管中的至少一个，并且可以临时或永久地断开相应的沟槽电容器。 可以通过暂时或永久地编程至少一个可编程电连接来调节电容器结构的总电容。

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