公开(公告)号：US08853752B2

公开(公告)日：2014-10-07

申请号：US13661188

申请日：2012-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： El Mehdi Bazizi ,  Alban Zaka ,  Gabriela Dilliway ,  Bo Bai

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

Abstract: In sophisticated semiconductor devices, transistors may be formed on the basis of an efficient strain-inducing mechanism by using an embedded strain-inducing semiconductor alloy. The strain-inducing semiconductor material may be provided as a graded material with a smooth strain transfer into the neighboring channel region in order to reduce the number of lattice defects and provide enhanced strain conditions, which in turn directly translate into superior transistor performance. The superior architecture of the graded strain-inducing semiconductor material may be accomplished by selecting appropriate process parameters during the selective epitaxial growth process without contributing to additional process complexity.

Abstract translation: 在复杂的半导体器件中，可以通过使用嵌入式应变诱导半导体合金，在有效的应变诱导机制的基础上形成晶体管。 应变诱导半导体材料可以被提供为具有平滑应变转移到相邻沟道区域中的渐变材料，以便减少晶格缺陷的数量并且提供增强的应变条件，这进而直接转化为优异的晶体管性能。 分级应变诱导半导体材料的优越结构可以通过在选择性外延生长工艺期间选择合适的工艺参数而不造成额外的工艺复杂性来实现。

公开(公告)号：US10134730B2

公开(公告)日：2018-11-20

申请号：US15642507

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Ran Yan ,  Bo Bai

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/306 ,  H01L21/3213

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor layer, forming a plurality of semiconductor fins on a surface of the semiconductor layer extending in parallel to each other along a first direction parallel to the surface of the semiconductor layer, and forming a plurality of gate electrodes comprising longitudinal portions extending parallel to the semiconductor fins along the first direction.

公开(公告)号：US20170309628A1

公开(公告)日：2017-10-26

申请号：US15642507

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Ran Yan ,  Bo Bai

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor layer, forming a plurality of semiconductor fins on a surface of the semiconductor layer extending in parallel to each other along a first direction parallel to the surface of the semiconductor layer, and forming a plurality of gate electrodes comprising longitudinal portions extending parallel to the semiconductor fins along the first direction.

公开(公告)号：US20160064286A1

公开(公告)日：2016-03-03

申请号：US14476031

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Gabriela Dilliway ,  Bo Bai ,  Peter Javorka ,  Dina H. Triyoso

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092

Abstract: Methods for fabricating integrated circuits and components thereof are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit is provided. The method includes providing a semiconductor substrate with a first gate structure and a second gate structure and a shallow trench isolation region outside of the first and second gate structures, depositing a mask on the first gate structure, and depositing a protection layer on the shallow trench isolation region to embed a STI protective cap.

Abstract translation: 提供了制造集成电路及其部件的方法。 根据示例性实施例，提供了一种用于制造集成电路的方法。 该方法包括在第一和第二栅极结构之外提供具有第一栅极结构和第二栅极结构以及浅沟槽隔离区域的半导体衬底，在第一栅极结构上沉积掩模，以及在浅沟槽上沉积保护层 隔离区域嵌入STI保护帽。

公开(公告)号：US20170250181A1

公开(公告)日：2017-08-31

申请号：US15054355

申请日：2016-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Ran Yan ,  Bo Bai

IPC: H01L27/088 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475

Abstract: A semiconductor device including a semiconductor layer, a plurality of semiconductor fins formed on a surface of the semiconductor layer and a plurality of gate electrodes formed over the surface of the semiconductor layer is provided. The semiconductor fins extend in parallel to each other along a first direction parallel to the surface of the semiconductor layer and have a first height in a second direction that is perpendicular to the first direction, and the gate electrodes comprise longitudinal portions extending parallel to the semiconductor fins along the first direction and, in particular, having a second height in the second direction lower than the first height.

公开(公告)号：US09748236B1

公开(公告)日：2017-08-29

申请号：US15054355

申请日：2016-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Ran Yan ,  Bo Bai

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475

Abstract: A semiconductor device including a semiconductor layer, a plurality of semiconductor fins formed on a surface of the semiconductor layer and a plurality of gate electrodes formed over the surface of the semiconductor layer is provided. The semiconductor fins extend in parallel to each other along a first direction parallel to the surface of the semiconductor layer and have a first height in a second direction that is perpendicular to the first direction, and the gate electrodes comprise longitudinal portions extending parallel to the semiconductor fins along the first direction and, in particular, having a second height in the second direction lower than the first height.

公开(公告)号：US08779525B2

公开(公告)日：2014-07-15

申请号：US13772401

申请日：2013-02-21

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823828

Abstract: A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.

Abstract translation: 在衬底上并入衬底和栅极线的互补金属氧化物半导体（CMOS）电路。 衬底包括n型场效应晶体管（n-FET）区域，p型场效应晶体管（p-FET）区域和设置在n-FET和p-FET区域之间的隔离区域。 栅极线包括n-FET栅极，p-FET栅极和从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极的栅极材料。 第一共形绝缘体覆盖栅极线，并且第二共形绝缘体位于位于p-FET栅极上方的第一共形绝缘体上，而不横向延伸穿过n-FET栅极。 用于产生不同类型应变的应变区形成在蚀刻到衬底的n-FET和p-FET区中的凹槽中。

公开(公告)号：US20140117417A1

公开(公告)日：2014-05-01

申请号：US13661188

申请日：2012-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： El Mehdi Bazizi ,  Alban Zaka ,  Gabriela Dilliway ,  Bo Bai

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

Abstract: In sophisticated semiconductor devices, transistors may be formed on the basis of an efficient strain-inducing mechanism by using an embedded strain-inducing semiconductor alloy. The strain-inducing semiconductor material may be provided as a graded material with a smooth strain transfer into the neighboring channel region in order to reduce the number of lattice defects and provide enhanced strain conditions, which in turn directly translate into superior transistor performance. The superior architecture of the graded strain-inducing semiconductor material may be accomplished by selecting appropriate process parameters during the selective epitaxial growth process without contributing to additional process complexity.

Abstract translation: 在复杂的半导体器件中，可以通过使用嵌入式应变诱导半导体合金，在有效的应变诱导机制的基础上形成晶体管。 应变诱导半导体材料可以被提供为具有平滑应变转移到相邻沟道区域中的渐变材料，以便减少晶格缺陷的数量并且提供增强的应变条件，这进而直接转化为优异的晶体管性能。 分级应变诱导半导体材料的优越结构可以通过在选择性外延生长工艺期间选择合适的工艺参数而不造成额外的工艺复杂性来实现。

公开(公告)号：US20130161759A1

公开(公告)日：2013-06-27

申请号：US13772401

申请日：2013-02-21

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

IPC: H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823828

Abstract: A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.

Abstract translation: 在衬底上并入衬底和栅极线的互补金属氧化物半导体（CMOS）电路。 衬底包括n型场效应晶体管（n-FET）区域，p型场效应晶体管（p-FET）区域和设置在n-FET和p-FET区域之间的隔离区域。 栅极线包括n-FET栅极，p-FET栅极和从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极的栅极材料。 第一共形绝缘体覆盖栅极线，并且第二共形绝缘体位于位于p-FET栅极上方的第一共形绝缘体上，而不横向延伸穿过n-FET栅极。 用于产生不同类型应变的应变区形成在蚀刻到衬底的n-FET和p-FET区中的凹槽中。