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    Method of forming a semiconductor device and resulting semiconductor devices
    4.
    发明授权
    Method of forming a semiconductor device and resulting semiconductor devices 有权
    形成半导体器件和所得半导体器件的方法

    公开(公告)号：US09324869B1

    公开(公告)日：2016-04-26

    申请号：US14613425

    申请日：2015-02-04

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Ran Yan ,  Alban Zaka ,  Jan Hoentschel

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L21/306 ,  H01L29/10 ,  H01L21/762 ,  H01L29/04 ,  H01L29/06

    CPC分类号： H01L29/7853 ,  H01L21/30608 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2029/7858

    摘要： The present disclosure provides, in various aspects, a method of forming a semiconductor device and accordingly formed semiconductor devices. In accordance with some illustrative embodiments herein, a fin is provided in an upper surface of a substrate, the fin having a height dimension and an initial width dimension. After forming a mask on the fin, wherein the mask only partially covers an upper surface of the fin, the fin is exposed to an etch process for removing material in accordance with the mask such that a channel portion connecting end portions of the fin is formed. Herein, a width dimension of the channel portion is smaller than a width dimension of the end portions. In accordance with some illustrative embodiments of the present disclosure, the channel portion may substantially have a cross-section of one of a triangular shape and a double-sigma shape.

    摘要翻译： 本公开在各个方面提供了一种形成半导体器件并相应地形成的半导体器件的方法。 根据这里的一些说明性实施例，在衬底的上表面中设置翅片，翅片具有高度尺寸和初始宽度尺寸。 在翅片上形成掩模之后，其中掩模仅部分地覆盖翅片的上表面，翅片暴露于根据掩模去除材料的蚀刻工艺，使得形成连接翅片的端部的通道部分 。 这里，通道部分的宽度尺寸小于端部的宽度尺寸。 根据本公开的一些示例性实施例，通道部分可以基本上具有三角形形状和双西格玛形状之一的横截面。

    LOW THERMAL BUDGET SCHEMES IN SEMICONDUCTOR DEVICE FABRICATION
    5.
    发明申请
    LOW THERMAL BUDGET SCHEMES IN SEMICONDUCTOR DEVICE FABRICATION 有权
    半导体器件制造中的低热预算方案

    公开(公告)号：US20140264349A1

    公开(公告)日：2014-09-18

    申请号：US14184863

    申请日：2014-02-20

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Nicolas Sassiat ,  Jan Hoentschel ,  Torben Balzer ,  Alban Zaka

    IPC分类号： H01L29/66 ,  H01L29/78

    CPC分类号： H01L21/26506 ,  H01L21/324 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： In aspects of the present invention, a method of forming a semiconductor device is disclosed, wherein amorphous regions are formed at an early stage during fabrication and the amorphous regions are conserved during subsequent processing sequences, and an intermediate semiconductor device structure with amorphous regions are provided at an early stage during fabrication. Herein a gate structure is provided over a semiconductor substrate and amorphous regions are formed adjacent the gate structure. Source/drain extension regions or source/drain regions are formed in the amorphous regions. In some illustrative embodiments, fluorine may be implanted into the amorphous regions. After the source/drain extension regions and/or the source/drain regions are formed, a rapid thermal anneal process is performed.

    摘要翻译： 在本发明的方面，公开了一种形成半导体器件的方法，其中在制造期间的早期阶段形成非晶区域，并且非晶区域在随后的处理序列期间保守，并且提供具有非晶区域的中间半导体器件结构 在制造的早期阶段。 这里，在半导体衬底上提供栅极结构，并且在栅极结构附近形成非晶区。 源极/漏极延伸区域或源极/漏极区域形成在非晶区域中。 在一些说明性实施例中，可以将氟注入到非晶区域中。 在形成源极/漏极延伸区域和/或源极/漏极区域之后，执行快速热退火工艺。

    PERFORMANCE ENHANCEMENT IN TRANSISTORS BY PROVIDING A GRADED EMBEDDED STRAIN-INDUCING SEMICONDUCTOR REGION WITH ADAPTED ANGLES WITH RESPECT TO THE SUBSTRATE SURFACE
    6.
    发明申请
    PERFORMANCE ENHANCEMENT IN TRANSISTORS BY PROVIDING A GRADED EMBEDDED STRAIN-INDUCING SEMICONDUCTOR REGION WITH ADAPTED ANGLES WITH RESPECT TO THE SUBSTRATE SURFACE 有权
    通过提供相对于基板表面的具有适配角的分级嵌入式应变诱导半导体区域在晶体管中的性能增强

    公开(公告)号：US20140117417A1

    公开(公告)日：2014-05-01

    申请号：US13661188

    申请日：2012-10-26

    申请人： GLOBALFOUNDRIES INC.

    发明人： El Mehdi Bazizi ,  Alban Zaka ,  Gabriela Dilliway ,  Bo Bai

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

    摘要： In sophisticated semiconductor devices, transistors may be formed on the basis of an efficient strain-inducing mechanism by using an embedded strain-inducing semiconductor alloy. The strain-inducing semiconductor material may be provided as a graded material with a smooth strain transfer into the neighboring channel region in order to reduce the number of lattice defects and provide enhanced strain conditions, which in turn directly translate into superior transistor performance. The superior architecture of the graded strain-inducing semiconductor material may be accomplished by selecting appropriate process parameters during the selective epitaxial growth process without contributing to additional process complexity.

    摘要翻译： 在复杂的半导体器件中，可以通过使用嵌入式应变诱导半导体合金，在有效的应变诱导机制的基础上形成晶体管。 应变诱导半导体材料可以被提供为具有平滑应变转移到相邻沟道区域中的渐变材料，以便减少晶格缺陷的数量并且提供增强的应变条件，这进而直接转化为优异的晶体管性能。 分级应变诱导半导体材料的优越结构可以通过在选择性外延生长工艺期间选择合适的工艺参数而不造成额外的工艺复杂性来实现。

    High-voltage devices integrated on semiconductor-on-insulator substrate
    7.
    发明授权
    High-voltage devices integrated on semiconductor-on-insulator substrate 有权

    公开(公告)号：US11552192B2

    公开(公告)日：2023-01-10

    申请号：US16876098

    申请日：2020-05-17

    申请人： GLOBALFOUNDRIES INC.

    发明人： Ruchil Kumar Jain ,  Alban Zaka

    IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L29/66

    摘要： The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a bulk substrate, a semiconductor layer above the bulk substrate, an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region on the bulk substrate, a gate dielectric between the source region and the drain region, the gate dielectric having a first portion on the bulk substrate and a second portion on the semiconductor layer, and a gate electrode above the gate dielectric.

    Thin body field effect transistor including a counter-doped channel area and a method of forming the same
    8.
    发明授权
    Thin body field effect transistor including a counter-doped channel area and a method of forming the same 有权

    公开(公告)号：US10283642B1

    公开(公告)日：2019-05-07

    申请号：US15957072

    申请日：2018-04-19

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Alban Zaka ,  Ignasi Cortes Mayol ,  Tom Herrmann ,  El Mehdi Bazizi ,  Luca Pirro

    IPC分类号： H01L29/786 ,  H01L29/08

    摘要： Manufacturing techniques and related semiconductor devices are disclosed in which the channel region of analog transistors and/or transistors operated at higher supply voltages may be formed on the basis of a very thin semiconductor layer in an SOI configuration by incorporating a counter-doped region into the channel region at the source side of the transistor. The counter-doped region may be inserted prior to forming the gate electrode structure. With this asymmetric dopant profile in the channel region, superior transistor performance may be obtained, thereby obtaining a performance gain for transistors formed on the basis of a thin semiconductor base material required for the formation of sophisticated fully depleted transistor elements.