公开(公告)号：US09379186B1

公开(公告)日：2016-06-28

申请号：US14610140

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qin Wang ,  Min-hwa Chi ,  Meixiong Zhao ,  Zhaoxu Shen ,  Haiting Wang ,  Lucas M. Salazar ,  Lan Yang

IPC: H01L21/302 ,  H01L21/461 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/4236 ,  H01L21/823412 ,  H01L21/823456 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628

Abstract: Methods for preparing CMOS transistors having longer effective gate lengths and the resulting devices are disclosed. Embodiments include forming a dummy gate bound by spacers on opposing sides thereof, on a substrate; removing the dummy gate to form a trench between the spacers; modifying a gate channel portion of the substrate between the spacers to form inner or outer sidewalls; depositing a conformal high-k dielectric layer on the modified gate channel portion; and forming a metal gate in the trench.

Abstract translation: 公开了制备具有更长有效栅极长度的CMOS晶体管的方法和所得到的器件。 实施例包括在基板上在其相对侧上形成由间隔物结合的虚拟栅极; 去除伪栅极以在间隔物之间​​形成沟槽; 修改间隔件之间的衬底的栅极通道部分以形成内侧壁或外侧壁; 在修改的栅极沟道部分上沉积保形高k电介质层; 并在沟槽中形成金属栅极。