公开(公告)号：US20200066593A1

公开(公告)日：2020-02-27

申请号：US16109258

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus LEE ,  Annie LEVESQUE ,  Qun GAO ,  Hui ZANG ,  Rishikesh KRISHNAN ,  Bharat KRISHNAN ,  Curtis DURFEE

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/532 ,  H01L23/535 ,  H01L21/02 ,  H01L29/40

Abstract: A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.

公开(公告)号：US20190295852A1

公开(公告)日：2019-09-26

申请号：US15925928

申请日：2018-03-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qun GAO ,  Naved SIDDIQUI ,  Ankur ARYA ,  John R. Sporre

IPC: H01L21/311 ,  H01L29/66 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/033 ,  H01L21/762

Abstract: The manufacture of a FinFET device includes the formation of a composite sacrificial gate. The composite sacrificial gate includes a sacrificial gate layer such as a layer of amorphous silicon, and an etch selective layer such as a layer of silicon germanium. The etch selective layer, which underlies the sacrificial gate layer, enables the formation of a gate cut opening having a controlled critical dimension that extends through the composite sacrificial gate.

公开(公告)号：US20190305105A1

公开(公告)日：2019-10-03

申请号：US15943272

申请日：2018-04-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qun GAO ,  Christopher NASSAR ,  Sugirtha KRISHNAMURTHY ,  Domingo Antonio FERRER LUPPI ,  John SPORRE ,  Shahab SIDDIQUI ,  Beth BAUMERT ,  Abu ZAINUDDIN ,  Jinping LIU ,  Tae Jeong LEE ,  Luigi PANTISANO ,  Heather LAZAR ,  Hui ZANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/423

Abstract: A method for controlling the gate length within a FinFET device to increase power performance and the resulting device are provided. Embodiments include forming a vertical gate to extend over a plurality of fins; depositing a respective oxide layer over each of a plurality of skirt regions formed at respective points of intersection of the vertical gate with the plurality of fins; and oxidizing each oxide layer to form a plurality of oxidized gate skirts.