公开(公告)号：US20180138177A1

公开(公告)日：2018-05-17

申请号：US15352963

申请日：2016-11-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus LEE ,  Bharat KRISHNAN ,  Jinping LIU ,  Hui ZANG ,  Judson Robert HOLT

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/3205 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/456

Abstract: Formation of band-edge contacts include, for example, providing an intermediate semiconductor structure comprising a substrate and a gate thereon and source/drain regions adjacent the gate, depositing a non-epitaxial layer on the source/drain regions, deposing a metal layer on the non-epitaxial layer, and forming metal alloy contacts from the deposited non-epitaxial layer and metal layer on the source/drain regions by annealing the deposited non-epitaxial layer and metal layer.

公开(公告)号：US20200066593A1

公开(公告)日：2020-02-27

申请号：US16109258

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus LEE ,  Annie LEVESQUE ,  Qun GAO ,  Hui ZANG ,  Rishikesh KRISHNAN ,  Bharat KRISHNAN ,  Curtis DURFEE

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/532 ,  H01L23/535 ,  H01L21/02 ,  H01L29/40

Abstract: A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.

公开(公告)号：US20180019313A1

公开(公告)日：2018-01-18

申请号：US15718958

申请日：2017-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus LEE ,  Jinping LIU ,  Ruilong XIE

IPC: H01L29/47 ,  H01L21/285 ,  H01L21/8238 ,  H01L21/266 ,  H01L29/40 ,  H01L27/092

CPC classification number: H01L29/47 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/401 ,  H01L29/78

Abstract: Methods for forming a semiconductor device having dual Schottky barrier heights using a single metal and the resulting device are provided. Embodiments include a semiconductor substrate having an n-FET region and a p-FET region each having source/drain regions; a titanium silicon (Ti—Si) intermix phase Ti liner on an upper surface of the n-FET region source/drain regions; and titanium silicide (TiSi) forming an upper surface of the p-FET region source/drain regions.

公开(公告)号：US20170256624A1

公开(公告)日：2017-09-07

申请号：US15060761

申请日：2016-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus LEE ,  Jinping LIU ,  Ruilong XIE

IPC: H01L29/47 ,  H01L21/266 ,  H01L21/8238 ,  H01L21/285 ,  H01L29/40 ,  H01L27/092

CPC classification number: H01L29/47 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/401 ,  H01L29/78

Abstract: Methods for forming a semiconductor device having dual Schottky barrier heights using a single metal and the resulting device are provided. Embodiments include providing a substrate having an n-FET region and a p-FET region, each region including a gate between source/drain regions; applying a mask over the n-FET region; selectively amorphizing a surface of the p-FET region source/drain regions while the n-FET region is masked; removing the mask; depositing a titanium-based metal over the n-FET and p-FET region source/drain regions; and microwave annealing.