公开(公告)号：US20180138177A1

公开(公告)日：2018-05-17

申请号：US15352963

申请日：2016-11-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus LEE ,  Bharat KRISHNAN ,  Jinping LIU ,  Hui ZANG ,  Judson Robert HOLT

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/3205 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/456

Abstract: Formation of band-edge contacts include, for example, providing an intermediate semiconductor structure comprising a substrate and a gate thereon and source/drain regions adjacent the gate, depositing a non-epitaxial layer on the source/drain regions, deposing a metal layer on the non-epitaxial layer, and forming metal alloy contacts from the deposited non-epitaxial layer and metal layer on the source/drain regions by annealing the deposited non-epitaxial layer and metal layer.

公开(公告)号：US20190043967A1

公开(公告)日：2019-02-07

申请号：US16026820

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert MULFINGER ,  Ryan SPORER ,  Timothy J. MCARDLE ,  Judson Robert HOLT

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L27/12 ,  H01L21/02 ,  H01L21/84 ,  H01L21/225

Abstract: Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.