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    SCALED GATE CONTACT AND SOURCE/DRAIN CAP
    1.
    发明申请
    SCALED GATE CONTACT AND SOURCE/DRAIN CAP 有权

    公开(公告)号：US20210066464A1

    公开(公告)日：2021-03-04

    申请号：US17097419

    申请日：2020-11-13

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hui ZANG ,  Ruilong XIE ,  Jae Gon LEE

    IPC: H01L29/417 ,  H01L29/08 ,  H01L29/51 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L23/528 ,  H01L23/522

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scaled gate contact and source/drain cap and methods of manufacture. The structure includes: a gate structure comprising an active region; source and drain contacts adjacent to the gate structure; a capping material over the source and drain contacts; a gate contact formed directly above the active region of the gate structure and over the capping material; a U-shape dielectric material around the gate contact, above the source and drain contacts; and a contact in direct electrical contact to the source and drain contacts.

    MIDDLE OF LINE STRUCTURES
    2.
    发明申请
    MIDDLE OF LINE STRUCTURES 审中-公开

    公开(公告)号：US20200176324A1

    公开(公告)日：2020-06-04

    申请号：US16204482

    申请日：2018-11-29

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hui ZANG ,  Ruilong XIE

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L21/311

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures; source and drain regions adjacent to respective gate structures of the plurality of gate structures; metallization features contacting selected source and drain regions; and recessed metallization features contacting other selected source and drain regions.

    METHOD OF CONCURRENTLY FORMING SOURCE/DRAIN AND GATE CONTACTS AND RELATED DEVICE
    6.
    发明申请
    METHOD OF CONCURRENTLY FORMING SOURCE/DRAIN AND GATE CONTACTS AND RELATED DEVICE 审中-公开

    公开(公告)号：US20180006028A1

    公开(公告)日：2018-01-04

    申请号：US15708911

    申请日：2017-09-19

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong XIE ,  Cheng CHI

    IPC: H01L27/088 ,  H01L29/45 ,  H01L29/08 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/285 ,  H01L29/66 ,  H01L21/8234

    Abstract: A method of concurrently forming source/drain contacts (CAs) and gate contacts (CBs) and device are provided. Embodiments include forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an ILD over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation of CAs adjacent a first portion of each PC and CBs over a second portion of the PCs; etching through the mask, forming trenches extending through the ILD down to a nitride capping layer formed over each PC and a trench silicide (TS) contact formed over each S/D region; selectively growing a metal capping layer over the TS contacts formed over the S/D regions; removing the nitride capping layer from the second portion of each PC; and metal filling the trenches, forming the CAs and CBs.

    METHODS TO FORM MULTI THRESHOLD-VOLTAGE DUAL CHANNEL WITHOUT CHANNEL DOPING
    7.
    发明申请
    METHODS TO FORM MULTI THRESHOLD-VOLTAGE DUAL CHANNEL WITHOUT CHANNEL DOPING 有权

    公开(公告)号：US20170221764A1

    公开(公告)日：2017-08-03

    申请号：US15014150

    申请日：2016-02-03

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hoon KIM ,  Min-gyu SUNG ,  Ruilong XIE ,  Chanro PARK

    IPC: H01L21/8234 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L27/088

    CPC classification number: H01L21/82345 ,  H01L21/28185 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517

    Abstract: Methods to form multi Vt channels, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices are disclosed. Embodiments include providing an interfacial-layer on a semiconductor substrate; forming a first high-k dielectric-layer on the interfacial-layer; forming a second high-k dielectric-layer and a first cap-layer, respectively, on the first high-k dielectric-layer; removing the second high-k dielectric and first cap layers in first and second regions; forming a second cap-layer on the first high-k dielectric-layer in the first and second regions and on the first cap-layer in a third region; performing an annealing process; removing the second cap-layer from all regions and the first cap-layer from the third region; forming a third high-k dielectric-layer over all regions; forming a work-function composition-layer and a barrier-layer on the third high-k dielectric-layer in all regions; removing the barrier-layer from the first region; and forming a gate electrode over all regions.

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