公开(公告)号：US12027580B2

公开(公告)日：2024-07-02

申请号：US17028178

申请日：2020-09-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anthony K. Stamper ,  Siva P. Adusumilli ,  Bruce W. Porth ,  John J. Ellis-Monaghan

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L29/0649 ,  H01L21/02505 ,  H01L21/7624 ,  H01L21/764

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor on insulator substrate with cavity structures and methods of manufacture. The structure includes: a bulk substrate with at least one rectilinear cavity structure; an insulator material sealing the at least one rectilinear cavity structure; and a buried insulator layer on the bulk substrate and over the at least one rectilinear cavity structure.

公开(公告)号：US11488980B2

公开(公告)日：2022-11-01

申请号：US17003179

申请日：2020-08-26

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. Adusumilli ,  Anthony K. Stamper ,  Bruce W. Porth ,  John J. Ellis-Monaghan

IPC: H01L27/12 ,  H01L21/762 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wafer with localized cavity structures and methods of manufacture. A structure includes a bulk substrate with localized semiconductor on insulator (SOI) regions and bulk device regions, the localized SOI regions includes multiple cavity structures and substrate material of the bulk substrate.

公开(公告)号：US11049932B2

公开(公告)日：2021-06-29

申请号：US16226640

申请日：2018-12-20

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Steven M. Shank ,  Mark David Levy ,  Bruce W. Porth

IPC: H01L29/06 ,  H01L29/732 ,  H01L21/762 ,  H01L21/763 ,  H01L21/765

Abstract: The present disclosure relates to isolation structures for semiconductor devices and, more particularly, to dual trench isolation structures having a deep trench and a shallow trench for electrically isolating integrated circuit (IC) components formed on a semiconductor substrate. The semiconductor isolation structure of the present disclosure includes a semiconductor substrate, a shallow trench isolation (STI) disposed over the semiconductor substrate, a deep trench isolation (DTI) with sidewalls extending from a bottom surface of the STI and terminating in the semiconductor substrate, a multilayer dielectric lining disposed on the sidewalls of the DTI, the multilayer dielectric lining including an etch stop layer positioned between inner and outer dielectric liners, and a filler material disposed within the DTI.