公开(公告)号：US12142686B2

公开(公告)日：2024-11-12

申请号：US17330780

申请日：2021-05-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Uzma Rana ,  Steven M. Shank ,  Mark D. Levy

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure having source/drain regions; at least one isolation structure within the source/drain regions in a substrate material; and semiconductor material on a surface of the at least one isolation structure in the source/drain regions.

公开(公告)号：US12028053B2

公开(公告)日：2024-07-02

申请号：US17643567

申请日：2021-12-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven M. Shank ,  Yves T. Ngu ,  Michael J. Zierak ,  Siva P. Adusumilli

IPC: H03K17/10 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/12 ,  H03K17/693

CPC classification number: H03K17/102 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/1203 ,  H03K17/693 ,  H03K2217/0018

Abstract: A structure includes a field effect transistor (FET) stack including a plurality of transistors over a buried insulator layer. A polysilicon isolation region is in a substrate below the FET stack and the buried insulator layer. A resistor network is in the polysilicon isolation region, the resistor network having a different resistivity than the polysilicon isolation region. The resistor network may include a resistive wire having a first width and a resistive pad within the resistive wire under each FET in the FET stack. Each resistive pad has a second width larger than the first width of the resistive wire. A length of the resistive wire is different aside each resistive pad to adjust a threshold voltage of an adjacent FET in the FET stack to a predetermined value to compensate for non-linear voltage distribution between an input and an output of the FET stack.

公开(公告)号：US20240088157A1

公开(公告)日：2024-03-14

申请号：US17942233

申请日：2022-09-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Michel Abou-Khalil ,  Steven M. Shank ,  Sarah McTaggart ,  Aaron Vallett ,  Rajendran Krishnasamy ,  Megan Lydon-Nuhfer

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/76286 ,  H01L21/84

Abstract: Semiconductor device structures with device isolation and methods of forming a semiconductor device structure with device isolation. The structure comprises a semiconductor substrate, a first semiconductor layer on the semiconductor substrate, a second semiconductor layer in a cavity in the first semiconductor layer, and a device structure including a doped region in the second semiconductor layer. The first semiconductor layer comprises a porous semiconductor material, and the second semiconductor layer comprises a single-crystal semiconductor material.

公开(公告)号：US11862511B2

公开(公告)日：2024-01-02

申请号：US17527716

申请日：2021-11-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli ,  Alvin Joseph

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76297 ,  H01L21/02595

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure includes a semiconductor substrate having a first trench, and a trench isolation region positioned in the first trench. The trench isolation region contains a dielectric material, the trench isolation region includes a second trench surrounded by the dielectric material, and the trench isolation region includes openings that penetrate through the dielectric material. A semiconductor layer is positioned in the second trench of the trench isolation region. The semiconductor layer contains a single-crystal semiconductor material.

公开(公告)号：US11848192B2

公开(公告)日：2023-12-19

申请号：US17124012

申请日：2020-12-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  Steven M. Shank ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/06

CPC classification number: H01L29/7373 ,  H01L29/0649 ,  H01L29/7371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

公开(公告)号：US11791334B2

公开(公告)日：2023-10-17

申请号：US17075056

申请日：2020-10-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  John J. Ellis-Monaghan ,  Anthony K. Stamper ,  Steven M. Shank ,  John J. Pekarik

IPC: H01L27/08 ,  H01L27/082 ,  H01L27/06 ,  H01L29/737 ,  H01L29/06

CPC classification number: H01L27/082 ,  H01L27/0647 ,  H01L29/0646 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

公开(公告)号：US11749717B2

公开(公告)日：2023-09-05

申请号：US17738179

申请日：2022-05-06

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Uzma Rana ,  Anthony K. Stamper ,  Johnatan A. Kantarovsky ,  Steven M. Shank ,  Siva P. Adusumilli

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/763 ,  H01L29/10

CPC classification number: H01L29/0653 ,  H01L21/763 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/823481 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7841

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.

公开(公告)号：US11719895B1

公开(公告)日：2023-08-08

申请号：US17679188

申请日：2022-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Nicholas Polomoff ,  Keith Donegan ,  Qizhi Liu ,  Steven M. Shank

IPC: G02B6/42 ,  H01S5/02251 ,  G02B1/00

CPC classification number: G02B6/4212 ,  G02B6/421 ,  G02B6/4245 ,  H01S5/02251 ,  G02B1/002

Abstract: Structures including an edge coupler, and methods of fabricating a structure that includes an edge coupler. The structure includes an edge coupler having a waveguide core with an end surface and a longitudinal axis. The end surface defines a plane tilted in a first direction at a first acute angle relative to the longitudinal axis and tilted in a second direction at a second acute angle relative to the longitudinal axis. The second direction differs from the first direction.

公开(公告)号：US20230223425A1

公开(公告)日：2023-07-13

申请号：US18188521

申请日：2023-03-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michael J. Zierak ,  Siva P. Adusumilli ,  Yves T. Ngu ,  Steven M. Shank

IPC: H01L21/20

CPC classification number: H01L28/20

Abstract: Embodiments of the disclosure provide a method, including forming a shallow trench isolation (STI) in a substrate. The method further includes doping the substrate with a noble dopant, thereby forming a disordered crystallographic layer under the STI. The method also includes converting the disordered crystallographic layer to a doped buried polysilicon layer under the STI and a high resistivity (HR) polysilicon layer under the doped buried polysilicon layer. The method includes forming a pair of contacts operatively coupled in a spaced manner to the doped buried polysilicon layer.

公开(公告)号：US11476289B2

公开(公告)日：2022-10-18

申请号：US16842080

申请日：2020-04-07

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. Adusumilli ,  Vibhor Jain ,  Alvin J. Joseph ,  Steven M. Shank

IPC: H01L27/146

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors with buried airgap mirror reflectors. The structure includes a photodetector and at least one airgap in a substrate under the photodetector.