公开(公告)号：US20250006842A1

公开(公告)日：2025-01-02

申请号：US18345001

申请日：2023-06-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： George Robert Mulfinger ,  Selina A. Mala ,  Pushparaj Dirgharaj Pathak ,  Chung Foong Tan

IPC: H01L29/78 ,  H01L21/84 ,  H01L27/12

Abstract: A structure includes a substrate, a first transistor on the substrate and a second transistor on the substrate. The second transistor is spaced apart from the first transistor by an isolation region. At least one stress-inducing liner is over the first transistor and the second transistor. An opening extends through at least one stress-inducing liner over at least the isolation region, and a dielectric layer is in at least a portion of the opening. The structure allows for local enhanced high-pressure deuterium (HPD) passivation, which increases threshold voltage of the transistors and improves hot carrier injection with no additional masking. A method of forming the structure is also provided.

公开(公告)号：US20240258376A1

公开(公告)日：2024-08-01

申请号：US18161219

申请日：2023-01-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Judson Robert Holt ,  George Robert Mulfinger

IPC: H01L29/10 ,  H01L21/8238

CPC classification number: H01L29/1054 ,  H01L21/823807

Abstract: An integrated circuit (IC) device is disclosed which includes a first transistor over a substrate. The first transistor includes a gate over the substrate and between a source region and a drain region. The transistor further includes a first region of vertically-graded silicon germanium (“SiGe”) adjacent a first side of a channel under the gate, and a second region of vertically-graded SiGe adjacent a second side of the channel. The channel includes substantially uniformly-graded SiGe.

公开(公告)号：US20240188287A1

公开(公告)日：2024-06-06

申请号：US18061538

申请日：2022-12-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： George Robert Mulfinger ,  Selina A. Mala ,  Shesh Mani Pandey ,  Adam S. Rosenfeld ,  Md Nasir Uddin Bhuyian

IPC: H10B20/20 ,  G11C17/16

CPC classification number: H01L27/11206 ,  G11C17/16

Abstract: A one-time programmable (OTP) fuse includes a trench isolation; a gate metal layer over the trench isolation; and a PN junction over the gate metal layer. More particularly, the OTP fuse may include a first terminal including a highly doped n-type polysilicon layer over the trench isolation, and a second terminal including a highly doped p-type polysilicon layer over the trench isolation. The highly doped n-type polysilicon layer contacts the highly doped p-type polysilicon layer, creating a PN junction and a fuse link defined in a portion of the gate metal layer between the trench isolation and the PN junction. The gate metal layer has a uniform thickness that allows better dimension control of the fuse link to reduce fuse programming current variability.

公开(公告)号：US11217678B2

公开(公告)日：2022-01-04

申请号：US16680196

申请日：2019-11-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： George Robert Mulfinger ,  Ryan Sporer ,  Rick J. Carter ,  Peter Baars ,  Hans-Jürgen Thees ,  Jan Höntschel

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.