公开(公告)号：US20210264973A1

公开(公告)日：2021-08-26

申请号：US16801458

申请日：2020-02-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Akhilesh Jaiswal ,  Ajey Poovannummoottil Jacob

IPC: G11C13/00 ,  G06F7/544 ,  G11C11/16

Abstract: Disclosed is a cell that integrates a pixel and a two-terminal non-volatile memory device. The cell can be selectively operated in write, read and functional computing modes. In the write mode, a first data value is stored the memory device. In the read mode, it is read from the memory device. In the functional computing mode, the pixel captures a second data value and a sensed change in an electrical parameter (e.g., voltage or current) on a bitline connected to the cell is a function of both the first and second data value. Also disclosed is an IC structure that includes an array of the cells and, when multiple cells in a given column are concurrently operated in the functional computing mode, the sensed total change in the electrical parameter on the bitline for the column is indicative of a result of a dot product computation.

公开(公告)号：US11120857B2

公开(公告)日：2021-09-14

申请号：US16720058

申请日：2019-12-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Akhilesh Jaiswal ,  Bipul C. Paul

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08

Abstract: Disclosed is a reference circuit having an even number m of groups of m parallel-connected magnetic tunnel junctions (MTJs). The MTJs in half of the groups are programmed to have parallel resistances (RP) and the MTJs in the other half are programmed to have anti-parallel resistances (RAP). Switches connect the groups in series, creating a series-parallel resistor network. The total resistance (RT) of the network has low variability and is essentially equal to half the sum of a nominal RP plus a nominal RAP and can be employed as a reference resistance (RREF). Under specific biasing conditions the series-parallel resistor network can generate a low variability reference parameter (XREF) that is dependent on this RREF. Also disclosed are an integrated circuit (IC) that includes the reference circuit and a magnetic random access memory (MRAM) structure, which uses XREF to determine stored data values in MRAM cells and associated methods.

公开(公告)号：US20210193204A1

公开(公告)日：2021-06-24

申请号：US16720058

申请日：2019-12-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Akhilesh Jaiswal ,  Bipul C. Paul

IPC: G11C11/16 ,  H01L43/08 ,  H01L27/22

Abstract: Disclosed is a reference circuit having an even number m of groups of m parallel-connected magnetic tunnel junctions (MTJs). The MTJs in half of the groups are programmed to have parallel resistances (RP) and the MTJs in the other half are programmed to have anti-parallel resistances (RAP). Switches connect the groups in series, creating a series-parallel resistor network. The total resistance (RT) of the network has low variability and is essentially equal to half the sum of a nominal RP plus a nominal RAP and can be employed as a reference resistance (RREF). Under specific biasing conditions the series-parallel resistor network can generate a low variability reference parameter (XREF) that is dependent on this RREF. Also disclosed are an integrated circuit (IC) that includes the reference circuit and a magnetic random access memory (MRAM) structure, which uses XREF to determine stored data values in MRAM cells and associated methods.

公开(公告)号：US11468146B2

公开(公告)日：2022-10-11

申请号：US16705434

申请日：2019-12-06

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Akhilesh Jaiswal ,  Ajey Poovannummoottil Jacob

IPC: G11C11/408 ,  G06F17/16 ,  H01L27/108 ,  H01L27/146 ,  G11C11/4094 ,  G11C17/06 ,  G11C13/00 ,  G06N3/063

Abstract: Disclosed are embodiments of an integrated circuit structure (e.g., a processing chip), which includes an array of integrated pixel and memory cells configured for deep in-sensor, in-memory computing (e.g., of neural networks). Each cell incorporates a memory structure (e.g., DRAM structure or a ROM structure) with a storage node, which stores a first data value (e.g., a binary weight value), and a sensor connected to a sense node, which outputs a second data value (e.g., an analog input value). Each cell is selectively operable in a functional computing mode during which the voltage level on a bit line is adjusted as a function of both the first data value and the second data value. Each cell is further selectively operable in a storage node read mode. Furthermore, depending upon the type of memory structure (e.g., a DRAM structure), each cell is selectively operable in a storage node write mode.

公开(公告)号：US10964367B1

公开(公告)日：2021-03-30

申请号：US16778548

申请日：2020-01-31

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Akhilesh Jaiswal ,  Ajey Poovannummoottil Jacob ,  Steven Soss

IPC: G11C11/16 ,  H01L27/22

Abstract: One illustrative MRAM device disclosed herein includes a first bit cell and a second bit cell. The first bit cell comprises a first access transistor and a first MTJ stack. The first MTJ stack comprises a first pinned layer and a first free layer, wherein the first pinned layer is connected to the first access transistor. The second bit cell comprises a second access transistor and a second MTJ stack. The second MTJ stack comprises a second pinned layer and a second free layer, wherein the second free layer is connected to the second access transistor.

公开(公告)号：US11195580B2

公开(公告)日：2021-12-07

申请号：US16801458

申请日：2020-02-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Akhilesh Jaiswal ,  Ajey Poovannummoottil Jacob

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16 ,  G06F7/544

Abstract: Disclosed is a cell that integrates a pixel and a two-terminal non-volatile memory device. The cell can be selectively operated in write, read and functional computing modes. In the write mode, a first data value is stored the memory device. In the read mode, it is read from the memory device. In the functional computing mode, the pixel captures a second data value and a sensed change in an electrical parameter (e.g., voltage or current) on a bitline connected to the cell is a function of both the first and second data value. Also disclosed is an IC structure that includes an array of the cells and, when multiple cells in a given column are concurrently operated in the functional computing mode, the sensed total change in the electrical parameter on the bitline for the column is indicative of a result of a dot product computation.

公开(公告)号：US11069402B1

公开(公告)日：2021-07-20

申请号：US16820801

申请日：2020-03-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Akhilesh Jaiswal ,  Ajey Poovannummoottil Jacob

IPC: G11C11/42 ,  G06F17/16 ,  G11C11/22 ,  G11C16/24 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: Disclosed is a cell that integrates a pixel and a three-terminal non-volatile memory device. The cell can be selectively operated in write, read and functional computing modes. In the write mode, a first data value is stored in the memory device. In the read mode, it is read from the memory device. In the functional computing mode, the pixel captures a second data value and a sensed change in an electrical parameter (e.g., voltage or current) on a bitline connected to the cell is a function of both the first and second data value. Also disclosed is an IC structure that includes an array of the cells and, when multiple cells in a given column are concurrently operated in the functional computing mode, the sensed total change in the electrical parameter on the bitline for the column is indicative of a result of a dot product computation.

公开(公告)号：US20210173894A1

公开(公告)日：2021-06-10

申请号：US16705434

申请日：2019-12-06

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Akhilesh Jaiswal ,  Ajey Poovannummoottil Jacob

IPC: G06F17/16 ,  H01L27/108 ,  H01L27/146 ,  G11C11/408 ,  G11C11/4094

Abstract: Disclosed are embodiments of an integrated circuit structure (e.g., a processing chip), which includes an array of integrated pixel and memory cells configured for deep in-sensor, in-memory computing (e.g., of neural networks). Each cell incorporates a memory structure (e.g., DRAM structure or a ROM structure) with a storage node, which stores a first data value (e.g., a binary weight value), and a sensor connected to a sense node, which outputs a second data value (e.g., an analog input value). Each cell is selectively operable in a functional computing mode during which the voltage level on a bit line is adjusted as a function of both the first data value and the second data value. Each cell is further selectively operable in a storage node read mode. Furthermore, depending upon the type of memory structure (e.g., a DRAM structure), each cell is selectively operable in a storage node write mode.