公开(公告)号：US11348870B2

公开(公告)日：2022-05-31

申请号：US16918053

申请日：2020-07-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jiehui Shu ,  Xiaoqiang Zhang ,  Haizhou Yin ,  Moosung M. Chae ,  Jinping Liu ,  Hui Zang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/525

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.

公开(公告)号：US11728192B2

公开(公告)日：2023-08-15

申请号：US17382415

申请日：2021-07-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Chenlong Miao ,  Haizhou Yin ,  Michael J. Wojtowecz

IPC: H01L21/67 ,  G06T7/00 ,  G01N23/2251

CPC classification number: H01L21/67288 ,  G01N23/2251 ,  G06T7/001 ,  G01N2223/071 ,  G01N2223/401 ,  G06T2207/10061 ,  G06T2207/30148

Abstract: An optical inspection is performed to detect potential defects within integrated circuit devices and a first electron-based inspection of less than all of the potential defects is performed to identify primary actual defects. A process window of manufacturing parameter settings used to manufacture the integrated circuit devices is identified and the integrated circuit devices manufactured using the manufacturing parameter settings inside the process window have less than a threshold number of the primary actual defects. To identify additional actual defects a second electron-based inspection is performed that is limited to selected ones of the potential defects in the integrated circuit devices that were manufactured using the manufacturing parameter settings inside the process window but were uninspected in the first electron-based inspection.

公开(公告)号：US20230024266A1

公开(公告)日：2023-01-26

申请号：US17382415

申请日：2021-07-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Chenlong Miao ,  Haizhou Yin ,  Michael J. Wojtowecz

IPC: H01L21/67 ,  G06T7/00 ,  G01N23/2251

Abstract: An optical inspection is performed to detect potential defects within integrated circuit devices and a first electron-based inspection of less than all of the potential defects is performed to identify primary actual defects. A process window of manufacturing parameter settings used to manufacture the integrated circuit devices is identified and the integrated circuit devices manufactured using the manufacturing parameter settings inside the process window have less than a threshold number of the primary actual defects. To identify additional actual defects a second electron-based inspection is performed that is limited to selected ones of the potential defects in the integrated circuit devices that were manufactured using the manufacturing parameter settings inside the process window but were uninspected in the first electron-based inspection.