公开(公告)号：US12087384B2

公开(公告)日：2024-09-10

申请号：US17668962

申请日：2022-02-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ming Yin ,  Bipul C. Paul ,  Nishtha Gaul ,  Shashank Nemawarkar

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C5/148

Abstract: The present disclosure relates to memory devices and, more particularly, to bias voltage generation circuit for memory devices and methods of operation. The voltage generation circuit includes: an internal voltage generator which providing a bias voltage to at least one internal node of a bias voltage generation circuitry; and at least one pre-charging circuitry providing a predefined bias voltage to at least one internal node including a distributed network of local drivers.

公开(公告)号：US20230253017A1

公开(公告)日：2023-08-10

申请号：US17668962

申请日：2022-02-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ming YIN ,  Bipul C. Paul ,  Nishtha Gaul ,  Shashank Nemawarkar

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C5/148

Abstract: The present disclosure relates to memory devices and, more particularly, to bias voltage generation circuit for memory devices and methods of operation. The voltage generation circuit includes: an internal voltage generator which providing a bias voltage to at least one internal node of a bias voltage generation circuitry; and at least one pre-charging circuitry providing a predefined bias voltage to at least one internal node including a distributed network of local drivers.

公开(公告)号：US11735257B2

公开(公告)日：2023-08-22

申请号：US17380093

申请日：2021-07-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nishtha Gaul ,  Bipul C. Paul ,  Akhilesh R. Jaiswal

IPC: G11C7/12 ,  G11C13/00 ,  H03K19/017 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/161 ,  G11C11/1673 ,  H03K19/01721 ,  G11C11/1659 ,  G11C2213/79

Abstract: Disclosed is a memory structure with reference-free single-ended sensing. The structure includes an array of non-volatile memory (NVM) cells (e.g., resistance programmable NVM cells) and a sense circuit connected to the array via a data line and a column decoder. The sense circuit includes field effect transistors (FETs) connected in parallel between an output node and a switch and inverters connected between the data line and the gates of the FETs, respectively. To determine the logic value of a stored bit, the inverters are used to detect whether or not a voltage drop occurs on the data line within a predetermined period of time. Using redundant inverters to control redundant FETs connected to the output node increases the likelihood that the occurrence of the voltage drop will be detected and captured at the output node, even in the presence of process and/or thermal variations. Also disclosed is a sensing method.

公开(公告)号：US20230027460A1

公开(公告)日：2023-01-26

申请号：US17380093

申请日：2021-07-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nishtha Gaul ,  Bipul C. Paul ,  Akhilesh R. Jaiswal

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  H03K19/017

Abstract: Disclosed is a memory structure with reference-free single-ended sensing. The structure includes an array of non-volatile memory (NVM) cells (e.g., resistance programmable NVM cells) and a sense circuit connected to the array via a data line and a column decoder. The sense circuit includes field effect transistors (FETs) connected in parallel between an output node and a switch and inverters connected between the data line and the gates of the FETs, respectively. To determine the logic value of a stored bit, the inverters are used to detect whether or not a voltage drop occurs on the data line within a predetermined period of time. Using redundant inverters to control redundant FETs connected to the output node increases the likelihood that the occurrence of the voltage drop will be detected and captured at the output node, even in the presence of process and/or thermal variations. Also disclosed is a sensing method.