公开(公告)号：US20230117591A1

公开(公告)日：2023-04-20

申请号：US17504051

申请日：2021-10-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Richard J. RASSEL ,  Johnatan A. KANTAROVSKY ,  Zhong-Xiang HE ,  Mark D. LEVY ,  Michel J. ABOU-KHALIL

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor device with a dual isolation structure and methods of manufacture. The structure includes: a dual isolation structure including semiconductor material; and an active device region including a channel material and a gate metal material over the channel material. The channel material is between the dual isolation structure and the gate metal material includes a bottom surface not extending beyond a sidewall of the dual isolation structure.

公开(公告)号：US20220399270A1

公开(公告)日：2022-12-15

申请号：US17343101

申请日：2021-06-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Venkata Narayana Rao VANUKURU ,  Zhong-Xiang HE

IPC: H01L23/522 ,  H01L23/528 ,  H01F17/00 ,  H01F41/04

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to series inductors and methods of manufacture. A structure includes a plurality of wiring levels each of which include a wiring structure connected in series to one another. A second wiring level being located above a first wiring level of the plurality of wiring levels. A wiring structure on the second wiring level being at least partially outside boundaries of the wiring structure of the first wiring level.

公开(公告)号：US20240186240A1

公开(公告)日：2024-06-06

申请号：US18438916

申请日：2024-02-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkata Narayana Rao VANUKURU ,  Zhong-Xiang HE

IPC: H01L23/522 ,  H01F17/00 ,  H01F41/04 ,  H01L23/528

CPC classification number: H01L23/5227 ,  H01F17/0013 ,  H01F41/041 ,  H01L23/5283

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to series inductors and methods of manufacture. A structure includes a plurality of wiring levels each of which include a wiring structure connected in series to one another. A second wiring level being located above a first wiring level of the plurality of wiring levels. A wiring structure on the second wiring level being at least partially outside boundaries of the wiring structure of the first wiring level.