公开(公告)号：US20230117591A1

公开(公告)日：2023-04-20

申请号：US17504051

申请日：2021-10-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Richard J. RASSEL ,  Johnatan A. KANTAROVSKY ,  Zhong-Xiang HE ,  Mark D. LEVY ,  Michel J. ABOU-KHALIL

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor device with a dual isolation structure and methods of manufacture. The structure includes: a dual isolation structure including semiconductor material; and an active device region including a channel material and a gate metal material over the channel material. The channel material is between the dual isolation structure and the gate metal material includes a bottom surface not extending beyond a sidewall of the dual isolation structure.

公开(公告)号：US20240088242A1

公开(公告)日：2024-03-14

申请号：US17943925

申请日：2022-09-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan A. KANTAROVSKY ,  Rebouh BENELBAR ,  Ajay RAMAN ,  Michel J. ABOU-KHALIL ,  Rajendran KRISHNASAMY ,  Randy L. WOLF

IPC: H01L29/417 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/41775 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-electron-mobility transistors and methods of manufacture. A structure includes: a semiconductor layer on a semiconductor material; a gate structure on the semiconductor layer; a drain region comprising the semiconductor layer and which is adjacent to the gate structure; an ohmic contact which includes at least one terminal connection connecting to the semiconductor material, the ohmic contact being adjacent to the drain region and spaced away from the gate structure; and a capacitance reducing structure adjacent to the drain region.

公开(公告)号：US20220028992A1

公开(公告)日：2022-01-27

申请号：US17498241

申请日：2021-10-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. STAMPER ,  Steven M. SHANK ,  Siva P. ADUSUMILLI ,  Michel J. ABOU-KHALIL

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked field effect transistors and methods of manufacture. The structure includes: at least one lower gate structure on a bottom of a trench formed in substrate material; insulator material partially filling trench and over the at least one lower gate structure; an epitaxial material on the insulator material and isolated from sidewalls of the trench; and at least one upper gate structure stacked vertically above the at least one lower gate structure and located on the epitaxial material.