公开(公告)号：US10283501B2

公开(公告)日：2019-05-07

申请号：US15447200

申请日：2017-03-02

Applicant: GaN Systems Inc.

Inventor： Thomas Macelwee ,  Greg P. Klowak ,  Howard Tweddle

IPC: H01L29/778 ,  H01L21/78 ,  H01L21/304 ,  H01L27/088 ,  H01L29/20 ,  H01L23/528 ,  H01L23/31 ,  H01L23/58 ,  H01L21/02

Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

公开(公告)号：US10985259B2

公开(公告)日：2021-04-20

申请号：US16212755

申请日：2018-12-07

Applicant: GaN Systems Inc.

Inventor： Thomas Macelwee

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L21/02 ,  H01L21/308

Abstract: GaN HEMT device structures and methods of fabrication are provided. A masking layer forms a p-dopant diffusion barrier and selective growth of p-GaN in the gate region, using low temperature processing, reduces deleterious effects of out-diffusion of p-dopant into the 2DEG channel. A structured AlxGa1-xN barrier layer includes a first thickness having a first Al %, and a second thickness having a second Al %, greater than the first Al %. At least part of the second thickness of the AlxGa1-xN barrier layer in the gate region is removed, before selective growth of p-GaN in the gate region. The first Al % and first thickness are selected to determine the threshold voltage Vth and the second Al % and second thickness are selected to determine the Rdson and dynamic Rdson of the GaN HEMT, so that each may be separately determined to improve device performance, and provide a smaller input FOM (Figure of Merit).

公开(公告)号：US10796998B1

公开(公告)日：2020-10-06

申请号：US16380318

申请日：2019-04-10

Applicant: GaN Systems Inc.

Inventor： Thomas Macelwee

IPC: H01L29/78 ,  H01L23/532 ,  H01L29/20 ,  H01L29/778 ,  H01L29/16 ,  H01L29/739

Abstract: Embedded packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a semiconductor die is embedded in a dielectric body comprising a dielectric polymer composition characterized by a conductivity transition temperature Tc, a first activation energy EaLow for conduction in a temperature range below Tc, and a second activation energy EaHigh for conduction in a temperature range above Tc. A test methodology is disclosed for selecting a dielectric epoxy composition having values of Tc, EaLow and EaHigh that provide a conduction value below a required reliability threshold, e.g. ≤5×10−13 S/cm, for a specified operating voltage and temperature. For example, the power semiconductor device comprises a GaN HEMT for operation at >100V wherein the package body is formed from a laminated dielectric epoxy composition for operation at >150 C, wherein Tc is ≥75 C, EaLow is ≤0.2 eV and EaHigh is ≤1 eV, for improved reliability for high voltage, high temperature operation.

公开(公告)号：US10249506B2

公开(公告)日：2019-04-02

申请号：US15712373

申请日：2017-09-22

Applicant: GaN Systems Inc.

Inventor： Thomas Macelwee ,  Greg P. Klowak ,  Howard Tweddle

IPC: H01L21/30 ,  H01L21/78 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L23/58 ,  H01L23/31 ,  H01L23/00 ,  C01B21/06 ,  H05B33/08 ,  C01G15/00 ,  H01L29/20

Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

公开(公告)号：USRE49603E1

公开(公告)日：2023-08-08

申请号：US16868632

申请日：2020-05-07

Applicant: GaN Systems Inc.

Inventor： Thomas Macelwee ,  Greg P. Klowak ,  Howard Tweddle

IPC: H01L21/304 ,  H01L27/088 ,  H01L29/20 ,  H01L23/528 ,  H01L23/31 ,  H01L23/58 ,  H01L21/02 ,  H01L29/778 ,  H01L21/78

CPC classification number: H01L27/088 ,  H01L21/3043 ,  H01L21/0254 ,  H01L21/02381 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/528 ,  H01L23/585 ,  H01L29/2003 ,  H01L29/778

Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

公开(公告)号：US11676899B2

公开(公告)日：2023-06-13

申请号：US17061839

申请日：2020-10-02

Applicant: GaN Systems Inc.

Inventor： Thomas Macelwee

IPC: H01L29/78 ,  H01L23/532 ,  H01L29/20 ,  H01L29/778 ,  H01L29/16 ,  H01L29/739

CPC classification number: H01L23/5329 ,  H01L29/2003 ,  H01L29/778 ,  H01L29/1608 ,  H01L29/7393 ,  H01L29/78

Abstract: Embedded packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a semiconductor die is embedded in a dielectric body comprising a dielectric polymer composition characterized by a conductivity transition temperature Tc, a first activation energy EaLow for conduction in a temperature range below Tc, and a second activation energy EaHigh for conduction in a temperature range above Tc. A test methodology is disclosed for selecting a dielectric epoxy composition having values of Tc, EaLow, and EaHigh that provide a conduction value below a required reliability threshold, e.g. ≤5×10−13 S/cm, for a specified operating voltage and temperature. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ≥100V wherein the package body is formed from a laminated dielectric epoxy composition for operation at >150 C, wherein Tc is ≥75 C, EaLow is ≤0.2 eV and EaHigh is ≤1 eV, for improved reliability for high voltage, high temperature operation.