Stack frame cache on a microprocessor chip
    1.
    发明授权
    Stack frame cache on a microprocessor chip 失效
    微处理器芯片上的堆栈缓存

    公开(公告)号:US4811208A

    公开(公告)日:1989-03-07

    申请号:US863878

    申请日:1986-05-16

    摘要: A plurality of global registers are provided on the microprocessor chip. One of a global registers is a frame pointer register containing the current frame pointer, and the remainder of the global registers are available to a current process as general registers. A plurality of floating point registers are also provided for use by the current process in execution of floating point arithmetic operations. A register set pool made up of a plurality of register sets is provided, each register set being comprised of a number of local registers. When a call instruction is decoded, a register set of local registers from the register set pool is allocated to the called procedure, and the frame pointer register is initialized. When a return instruction is decoded, the register set is freed for allocation to another procedure called by a subsequent call instruction. If the register set pool is depleted a register set associated with a previous procedure is saved in the main memory, and that register set is allocated to the current procedure. The local registers in a register set associated with a procedure contain linkage information including a pointer to the previous frame and an instruction pointer, thus enabling most call and return instructions to execute without needing any references to off-chip memory.

    摘要翻译: 在微处理器芯片上提供多个全局寄存器。 全局寄存器之一是包含当前帧指针的帧指针寄存器,其余的全局寄存器作为通用寄存器可用于当前进程。 还提供了多个浮点寄存器供当前进程在浮点算术运算中使用。 提供由多个寄存器组构成的寄存器组池,每个寄存器组由多个本地寄存器组成。 当调用指令被解码时,寄存器组池的本地寄存器的寄存器组被分配给被调用的程序,并且帧指针寄存器被初始化。 当返回指令被解码时,寄存器组被释放以分配给由后续调用指令调用的另一过程。 如果寄存器集合池耗尽,则与先前过程相关联的寄存器集保存在主存储器中,并且该寄存器集被分配给当前过程。 与过程相关联的寄存器集中的本地寄存器包含链接信息,包括指向前一帧的指针和指令指针,从而使得大多数调用和返回指令执行而不需要对片外存储器的任何引用。

    Register scorboarding on a microprocessor chip
    2.
    发明授权
    Register scorboarding on a microprocessor chip 失效
    在微处理器芯片上注册scorboarding

    公开(公告)号:US4891753A

    公开(公告)日:1990-01-02

    申请号:US935193

    申请日:1986-11-26

    IPC分类号: G06F9/28 G06F9/22 G06F9/38

    CPC分类号: G06F9/3838 G06F9/3836

    摘要: When a load instruction is encountered, a read operation is sent to the bus control logic, the register is marked as busy, and execution proceeds to the next instruction. When an instruction is executed, it proceeds providing that its source and destination registers are not marked busy; otherwise the instruction is retried. When data are returned as the result of a read operation, the destination register(s) are marked as not busy.

    摘要翻译: 当遇到加载指令时,读操作被发送到总线控制逻辑,寄存器被标记为忙,并且执行进行到下一条指令。 当执行指令时,继续执行其源和目标寄存器未标记为忙; 否则将重试该指令。 当作为读取操作的结果返回数据时,目标寄存器被标记为不忙。