公开(公告)号：US11456364B2

公开(公告)日：2022-09-27

申请号：US17029446

申请日：2020-09-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ketankumar H. Tailor ,  Peter Baars ,  Ruchil K. Jain

IPC: H01L29/40 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06

Abstract: Embodiments of the disclosure provide an integrated circuit device and related methods. The disclosure may provide a transistor device, including: a gate structure; a drain extension region extending laterally from partially under the gate structure to a drain region; and a gate spacer located over the drain extension region. A silicide-blocking layer is over and in contact with the gate spacer. The silicide-blocking layer has a first end over the gate structure and a second, opposing end over the drain extension region. The structure also provides a conductive field plate, including a conductive layer over and in contact with the silicide-blocking layer. A field plate contact is formed on the conductive field plate.

公开(公告)号：US20230395607A1

公开(公告)日：2023-12-07

申请号：US17830830

申请日：2022-06-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Peter Baars ,  Viorel Ontalus ,  Ketankumar H. Tailor ,  Michael Zier ,  Crystal R. Kenney ,  Judson Holt

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/1207 ,  H01L21/84 ,  H01L29/66242

Abstract: Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.

公开(公告)号：US12113070B2

公开(公告)日：2024-10-08

申请号：US17830830

申请日：2022-06-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Peter Baars ,  Viorel Ontalus ,  Ketankumar H. Tailor ,  Michael Zier ,  Crystal R. Kenney ,  Judson Holt

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/1207 ,  H01L21/84 ,  H01L29/66242

Abstract: Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.

公开(公告)号：US20220093751A1

公开(公告)日：2022-03-24

申请号：US17029446

申请日：2020-09-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ketankumar H. Tailor ,  Peter Baars ,  Ruchil K. Jain

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49

Abstract: Embodiments of the disclosure provide an integrated circuit device and related methods. The disclosure may provide a transistor device, including: a gate structure; a drain extension region extending laterally from partially under the gate structure to a drain region; and a gate spacer located over the drain extension region. A silicide-blocking layer is over and in contact with the gate spacer. The silicide-blocking layer has a first end over the gate structure and a second, opposing end over the drain extension region. The structure also provides a conductive field plate, including a conductive layer over and in contact with the silicide-blocking layer. A field plate contact is formed on the conductive field plate.