公开(公告)号：US08779953B1

公开(公告)日：2014-07-15

申请号：US13955499

申请日：2013-07-31

Applicant: Google Inc.

Inventor： Clemenz Portmann ,  Shahriar Rabii ,  Donald Charles Stark

IPC: H03M1/10

CPC classification number: H03M1/109 ,  H03M1/662

Abstract: A method and device for testing a digital-to-analog converter is provided. The method may include configuring a decoder to address an individual unit cell of a plurality of unit cells of a digital-to-analog converter. The configured decoder may select a particular unit cell of the plurality of unit cells for testing. The selected unit cell may have digital and analog circuitry. A bias current of the selected unit cell may be increased. The increased bias current of the selected unit cell may be greater during the testing than during normal operation. A test logic signal may be applied to the selected unit cell. In response to the test logic signal, an output signal may be output from the selected unit cell logic circuitry of the digital-to-analog converter. A device may include logic circuitry configured to select an individual unit cell for testing and a current generating circuitry.

Abstract translation: 提供了一种用于测试数模转换器的方法和装置。 该方法可以包括配置解码器以寻址数模转换器的多个单位单元的单个单元。 配置的解码器可以选择多个单位单元中的特定单元以进行测试。 所选择的单元可以具有数字和模拟电路。 可以增加所选择的单元电池的偏置电流。 所选择的单元电池的增加的偏置电流在测试期间可能比在正常操作期间更大。 测试逻辑信号可以应用于所选择的单位单元。 响应于测试逻辑信号，输出信号可以从数模转换器的所选择的单元电路逻辑电路输出。 设备可以包括被配置为选择用于测试的单个单元单元的逻辑电路和当前生成电路。

公开(公告)号：US09270282B2

公开(公告)日：2016-02-23

申请号：US14138506

申请日：2013-12-23

Applicant: Google Inc.

Inventor： Clemenz Portmann ,  Donald Charles Stark

IPC: G06F1/08 ,  H03L7/06 ,  H03K5/14

CPC classification number: H03L7/06 ,  H03K5/14 ,  H03L7/00

Abstract: A clock signal for use by a circuit can be switched between clocks glitchlessly. A series of delay devices are connected in series based on an integral timing ratio. The integral timing ratio can be based on a ratio of the one of the clock's frequency or period to the other's frequency or period. When a clock select signal is received, the select signal is qualified and then delayed an amount of time based on the integral timing ratio, using the delay devices. The number of delay devices in each series can be the next largest integer to the integral timing ratio, plus one. The clock signal can then be glitchlessly switched from one clock to the other.

Abstract translation: 电路使用的时钟信号可在时钟之间无缝地切换。 一系列延迟装置基于积分时序比率串联连接。 积分时序比可以基于时钟的频率或周期中的一个与另一个的频率或周期的比率。 当接收到时钟选择信号时，选择信号被限定，然后使用延迟装置基于积分时序比延迟一定量的时间。 每个系列中的延迟器件的数量可以是整数定时比的下一个最大整数，加上一个。 时钟信号可以无缝地从一个时钟切换到另一个时钟。

公开(公告)号：US20150180484A1

公开(公告)日：2015-06-25

申请号：US14138506

申请日：2013-12-23

Applicant: Google Inc.

Inventor： Clemenz Portmann ,  Donald Charles Stark

IPC: H03L7/06 ,  H03K5/14

CPC classification number: H03L7/06 ,  H03K5/14 ,  H03L7/00

Abstract: A clock signal for use by a circuit can be switched between clocks glitchlessly. A series of delay devices are connected in series based on an integral timing ratio. The integral timing ratio can be based on a ratio of the one of the clock's frequency or period to the other's frequency or period. When a clock select signal is received, the select signal is qualified and then delayed an amount of time based on the integral timing ratio, using the delay devices. The number of delay devices in each series can be the next largest integer to the integral timing ratio, plus one. The clock signal can then be glitchlessly switched from one clock to the other.

Abstract translation: 电路使用的时钟信号可在时钟之间无缝地切换。 一系列延迟装置基于积分时序比率串联连接。 积分时序比可以基于时钟的频率或周期中的一个与另一个的频率或周期的比率。 当接收到时钟选择信号时，选择信号被限定，然后使用延迟装置基于积分时序比延迟一定量的时间。 每个系列中的延迟器件的数量可以是整数定时比的下一个最大整数，加上一个。 时钟信号可以无缝地从一个时钟切换到另一个时钟。

公开(公告)号：US08930594B1

公开(公告)日：2015-01-06

申请号：US13963367

申请日：2013-08-09

Applicant: Google Inc.

Inventor： Paul Kingsley Rodman ,  Donald Charles Stark

IPC: G06F3/00 ,  G06F5/00 ,  G06F13/38 ,  G06F13/10

CPC classification number: G06F13/4022

Abstract: Described is an integrated circuit (IC) that allows for communication between any input/output (I/O) pin and onboard peripherals. Accordingly, the resultant IC can be easily documented and connections between I/O pins and peripherals can be managed for each peripheral independently. The IC may include one or more sets of hardwired connections that provide a connection between of any I/O pin and any onboard peripheral. The hardwired connections may include the use of one or more crossbars. This increases the overall functionality and potential applications for an IC as the only limitation on peripheral connectivity is the number of I/O pins.

Abstract translation: 描述了允许任何输入/输出（I / O）引脚和板载外设之间通信的集成电路（IC）。 因此，可以容易地记录所得到的IC，并且可以独立地为每个外设管理I / O引脚和外围设备之间的连接。 IC可以包括提供任何I / O引脚和任何板载外设之间的连接的一组或多组硬连线连接。 硬连线可能包括使用一个或多个横梁。 这增加了IC的总体功能和潜在应用，因为对外设连接性的唯一限制是I / O引脚的数量。