公开(公告)号：US20210240945A1

公开(公告)日：2021-08-05

申请号：US17049031

申请日：2018-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul STRACHAN ,  Dejan S. MILOJICIC ,  Martin FOLTIN ,  Sai Rahul CHALAMALASETTI ,  Amit S. SHARMA

IPC: G06J1/00 ,  G11C13/00 ,  G06F13/40 ,  G06F15/80 ,  G06F17/16

Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.