公开(公告)号：US20210240945A1

公开(公告)日：2021-08-05

申请号：US17049031

申请日：2018-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul STRACHAN ,  Dejan S. MILOJICIC ,  Martin FOLTIN ,  Sai Rahul CHALAMALASETTI ,  Amit S. SHARMA

IPC: G06J1/00 ,  G11C13/00 ,  G06F13/40 ,  G06F15/80 ,  G06F17/16

Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.

公开(公告)号：US20190129864A1

公开(公告)日：2019-05-02

申请号：US15799153

申请日：2017-10-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Paolo FARABOSCHI ,  Dejan S. MILOJICIC ,  Kirk M. BRESNIKER

IPC: G06F12/14 ,  G06F12/1027 ,  G06F12/1009

Abstract: According to examples, a system may include a central processing unit (CPU) and a capability enforcement controller in communication with the CPU. The capability enforcement controller may be separate from the CPU and may implement capability processing functions that control capabilities. Capabilities may be defined as unforgeable tokens of authority that protect access by the CPU to a physical address at which the data is stored in a memory.