公开(公告)号：US20190235889A1

公开(公告)日：2019-08-01

申请号：US15884030

申请日：2018-01-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Geoffrey NDU ,  Dejan MILOJICIC ,  Sai Rahul CHALAMALASETTI

IPC: G06F9/455 ,  H04L29/06 ,  G06F17/16

Abstract: An example system includes at least one memristive dot product engine (DPE) having at least one resource, the DPE further having a physical interface and a controller, the controller being communicatively coupled to the physical interface, the physical interface to communicate with the controller to access the DPE, and at least one replicated interface, each replicated interface being associated with a virtual DPE, the replicated interface with communicatively coupled to the controller. The controller is to allocate timeslots to the virtual DPE through the associated replicated interface to allow the virtual DPE access to the at least one resource.

公开(公告)号：US20210240945A1

公开(公告)日：2021-08-05

申请号：US17049031

申请日：2018-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul STRACHAN ,  Dejan S. MILOJICIC ,  Martin FOLTIN ,  Sai Rahul CHALAMALASETTI ,  Amit S. SHARMA

IPC: G06J1/00 ,  G11C13/00 ,  G06F13/40 ,  G06F15/80 ,  G06F17/16

Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.