公开(公告)号：US20190189174A1

公开(公告)日：2019-06-20

申请号：US16062578

申请日：2017-12-17

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Miao HU ,  John Paul STRACHAN ,  Zhiyong LI ,  Stanley WILLIAMS

IPC: G11C11/16 ,  G11C13/00

CPC classification number: G11C11/1659 ,  G11C11/1677 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0064 ,  G11C2213/71 ,  G11C2213/77

Abstract: Example implementations of the present disclosure relate to improved computational accuracy in a crossbar array. An example system may include a crossbar array, having a plurality of memory elements at junctions, usable in performance of computations. The example system may further include a calculate engine to calculate ideal conductance of memory elements at a plurality of junctions of the crossbar array and a determine engine to determine conductance of the memory elements at the plurality of junctions of the crossbar array. An adjust engine of the example system may be used to adjust conductance of at least one memory element to improve computational accuracy by reduction of a difference between the ideal conductance and the determined conductance of the at least one memory element.

公开(公告)号：US20210240945A1

公开(公告)日：2021-08-05

申请号：US17049031

申请日：2018-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul STRACHAN ,  Dejan S. MILOJICIC ,  Martin FOLTIN ,  Sai Rahul CHALAMALASETTI ,  Amit S. SHARMA

IPC: G06J1/00 ,  G11C13/00 ,  G06F13/40 ,  G06F15/80 ,  G06F17/16

Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.

公开(公告)号：US20180364785A1

公开(公告)日：2018-12-20

申请号：US16062882

申请日：2015-12-18

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Miao HU ,  Tsung-Ching HUANG ,  Chin-Hui CHEN ,  Raymond G BEAUSOLEIL ,  John Paul STRACHAN

IPC: G06F1/32 ,  G11C13/00 ,  G06N3/04

Abstract: In one example, a device to process analog sensor data is described. For example, a device may include at least one analog sensor to generate a first set of analog voltage signals and a crossbar array including a plurality of memristors. In one example, the crossbar array is to receive an input vector of the first set of analog voltage signals, generate an output vector comprising a second set of analog voltage signals that is based upon a dot product of the input vector and a matrix comprising resistance values of the plurality of memristors, detect a pattern of the output vector, and activate a processor upon a detection of the pattern.

公开(公告)号：US20210241068A1

公开(公告)日：2021-08-05

申请号：US17049032

申请日：2018-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Martin FOLTIN ,  John Paul STRACHAN ,  Sergey SEREBRYAKOV

IPC: G06N3/04 ,  G06N3/10 ,  G06N3/08

Abstract: A convolutional neural network system includes a first part of the convolutional neural network comprising an initial processor configured to process an input data set and store a weight factor set in the first part of the convolutional neural network; and a second part of the convolutional neural network comprising a main computing system configured to process an export data set provided from the first part of the convolutional neural network.

公开(公告)号：US20240046988A1

公开(公告)日：2024-02-08

申请号：US17876471

申请日：2022-07-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： GIACOMO PEDRETTI ,  Catherine GRAVES ,  Sergey SEREBRYAKOV ,  John Paul STRACHAN

IPC: G11C15/04 ,  G11C7/06 ,  G11C7/16 ,  H03M1/18

CPC classification number: G11C15/04 ,  G11C7/062 ,  G11C7/16 ,  H03M1/181

Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for providing a differentiable content addressable memory (aCAM) that implements an analog input analog storage and analog output learning memory. The analog output of the differentiable CAM can provide input to a learning algorithm, which may compute the gradients in comparison to historic values and reduce data inaccuracies and power consumption.

公开(公告)号：US20180089146A1

公开(公告)日：2018-03-29

申请号：US15280903

申请日：2016-09-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Miao HU ,  John Paul STRACHAN ,  Naveen MURALIMANOHAR

IPC: G06F17/14 ,  G06F17/15

CPC classification number: G06F17/14 ,  G06F17/15 ,  G06F17/156

Abstract: Examples herein relate to convolution accelerators. An example convolution accelerator may include a transformation crossbar array programmed to calculate a Fourier Transformation of a first vector with a transformation matrix and a Fourier Transformation of a second vector with the transformation matrix. A circuit of the example convolution accelerator may multiply the Fourier Transformation of the first vector with the Fourier Transformation of the second vector to calculate a product vector. The example convolution accelerator may have an inverse transformation crossbar array programmed to calculate an Inverse Fourier Transformation of the product vector according to an inverse transformation matrix.

公开(公告)号：US20170316827A1

公开(公告)日：2017-11-02

申请号：US15521542

申请日：2014-10-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ning GE ,  Jianhua YANG ,  John Paul STRACHAN ,  Miao HU

IPC: G11C13/00 ,  G06F17/16 ,  G06F17/11

CPC classification number: G11C13/0069 ,  G06F17/11 ,  G06F17/16 ,  G06G7/16 ,  G11C7/1006 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/15 ,  G11C2213/77

Abstract: A method of obtaining a dot product includes applying a number of first voltages to a corresponding number of row lines within a memristive cross-bar array to change the resistive values of a corresponding number of memristors located a junctions between the row lines and a number of column lines. The first voltages define a corresponding number of values within a matrix, respectively. The method further includes applying a number of second voltages to a corresponding number of the row lines within the memristive cross-bar array. The second voltages define a corresponding number of vector values. The method further includes collecting the output currents from the column lines. The collected output currents define the dot product.

公开(公告)号：US20170249989A1

公开(公告)日：2017-08-31

申请号：US15500075

申请日：2014-11-18

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul STRACHAN ,  Glen E. MONTGOMERY ,  Ning GE ,  Miao HU ,  Jianhua YANG

IPC: G11C13/00 ,  G01J1/00 ,  G06G7/16

CPC classification number: G11C13/0069 ,  G01J1/00 ,  G06G7/16 ,  G11C7/062 ,  G11C7/067 ,  G11C7/1006 ,  G11C11/1673 ,  G11C13/0021 ,  G11C13/004 ,  G11C2013/0057 ,  G11C2013/0088 ,  G11C2213/77

Abstract: A method of obtaining a dot product using a memristive dot product engine with a nulling amplifier includes applying a number of programming voltages to a number of row lines within a memristive crossbar array to change the resistance values of a corresponding number of memristors located at intersections between the row lines and a number of column lines. The method also includes applying a number of reference voltages to the number of the row lines and applying a number of operating voltages to the number of the row lines. The operating voltages represent a corresponding number of vector values. The method also includes determining an array output based on a reference output and an operating output collected from the number of column lines.

公开(公告)号：US20170221560A1

公开(公告)日：2017-08-03

申请号：US15500500

申请日：2015-04-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Miao HU ,  John Paul STRACHAN ,  Ning GE ,  Jianhua YANG

IPC: G11C13/00 ,  G06N7/00

CPC classification number: G11C13/0021 ,  G06F7/588 ,  G06F17/18 ,  G06G7/122 ,  G06N7/005

Abstract: An example apparatus includes a crossbar array of signal lines and control lines. The example apparatus also includes an input controller in circuit with the control lines. The input control is to select one of the control lines. The example apparatus also includes first resistive elements connected between corresponding ones of the control lines and corresponding ones of the signal lines. The first resistive elements have first conductances set to operate as a matrix of probabilities that define a fixed transition kernel of a Markov Chain. The example apparatus also includes second resistive elements in circuit with the signal lines. The second resistive elements have second conductances set to select one of the signal lines exclusive of others of the signal lines based on a subset of the probabilities in the matrix of the probabilities.