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公开(公告)号：US10795782B2
公开(公告)日：2020-10-06
申请号：US15942925
申请日：2018-04-02
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Dejan S. Milojicic , Keith Packard , Michael Woodacre , Andrew R. Wheeler
Abstract: Example implementations relate to an apparatus to support providing a computing service to a client including transferring control between a primary data processing system and a secondary data processing system in response to an event; the primary data processing system comprising a processor and associated memory and the secondary data processing system comprising a processor and associated memory; the apparatus comprising: circuitry to identify restoration data; the restoration data comprising at least data associated with at least one predetermined type of memory operation of the memory associated with the primary data processing system, and circuitry to output any identified restoration data for storage in the memory associated with the processor of the secondary data processing system.
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公开(公告)号：US20170315729A1
公开(公告)日：2017-11-02
申请号：US15518209
申请日：2014-10-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Russ W. Herrell , Greg Astfalk , Gregg B. Lesartre , Andrew R. Wheeler
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0604 , G06F3/0679 , G06F12/0238 , G06F2212/7207
Abstract: Example implementations relate to a method of tracking data in a non-volatile memory device (NVM) device. A meta-data block from the NVM device is obtained, where the meta-data block includes meta-data. The meta-data block from the NVM device is used to track an associated data object, meta-data in the data block, a user data block, a meta-data block, or an additional data block. The meta-data block from the NVM device is used to point to the associated data object, the meta-data in the data block, the user data block, the meta-data block, or the additional data block. The meta-data block from the NVM device is further used to link the associated data object, the meta-data in the data block, the user data block, the meta-data block, or the additional data block.
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公开(公告)号：US10235078B2
公开(公告)日：2019-03-19
申请号：US15518209
申请日：2014-10-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Russ W. Herrell , Greg Astfalk , Gregg B. Lesartre , Andrew R. Wheeler
Abstract: Example implementations relate to a method of tracking data in a non-volatile memory device (NVM) device. A meta-data block from the NVM device is obtained, where the meta-data block includes meta-data. The meta-data block from the NVM device is used to track an associated data object, meta-data in the data block, a user data block, a meta-data block, or an additional data block. The meta-data block from the NVM device is used to point to the associated data object, the meta-data in the data block, the user data block, the meta-data block, or the additional data block. The meta-data block from the NVM device is further used to link the associated data object, the meta-data in the data block, the user data block, the meta-data block, or the additional data block.
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公开(公告)号：US10452498B2
公开(公告)日：2019-10-22
申请号：US14901559
申请日：2013-06-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Gregg B. Lesartre , Dale C. Morris , Gary Gostin , Russ W. Herrell , Andrew R. Wheeler , Blaine D. Gaither
Abstract: A computing system can include a processor and a persistent main memory including a fault tolerance capability. The computing system can also include a memory controller to store data in the persistent main memory and create redundant data. The memory controller can also store the redundant data remotely with respect to the persistent main memory. The memory controller can further access the redundant data during failure of the persistent main memory.
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公开(公告)号：US09921747B2
公开(公告)日：2018-03-20
申请号：US15114427
申请日：2014-01-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Andrew R. Wheeler , Boris Zuckerman , Greg Astfalk , Russ W. Herrell
CPC classification number: G06F3/0604 , G06F3/06 , G06F3/0631 , G06F3/0638 , G06F3/0647 , G06F3/0683 , G06F12/0223 , G06F12/0802 , G06F13/16 , G06F13/1694 , G06F13/4068 , G06F2212/60 , Y02D10/14 , Y02D10/151
Abstract: A unifying memory controller (UMC) to send and receive data to and from a local host. The UMC also may manage data placement and retrieval by using an address mapper. The UMC may also selectively provide power to a plurality of memory locations. The UMC may also manage data placement based on a policy that can make use of a property stored in the metadata storage location. The property may be a property describing the data that is being managed. The UMC also may use its own local cache that may store copies of data managed by the circuit.
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Patent Agency Ranking
公开(公告)号：US11128531B2
公开(公告)日：2021-09-21
申请号：US15967583
申请日：2018-04-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Dejan S Milojicic , Sharad Singhal , Andrew R. Wheeler , Michael S. Woodacre
IPC: H04L12/24 , G06F11/34 , H04L12/911 , H04L12/26 , G06F11/30
Abstract: Systems and methods for dynamically and programmatically controlling hardware and software to optimize bandwidth and latency across partitions in a computing system are discussed herein. In various embodiments, performance within a partitioned computing system may be monitored and used to automatically reconfigure the computing system to optimize aggregate bandwidth and latency. Reconfiguring the computing system may comprise reallocating hardware resources among partitions, programming firewalls to enable higher bandwidth for specific inter-partition traffic, switching programming models associated with individual partitions, starting additional instances of one or more applications running on the partitions, and/or one or more other operations to optimize the overall aggregate bandwidth and latency of the system.
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公开(公告)号：US20190303249A1
公开(公告)日：2019-10-03
申请号：US15942925
申请日：2018-04-02
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Dejan S. Milojicic , Keith Packard , Michael Woodacre , Andrew R. Wheeler
IPC: G06F11/14
Abstract: Example implementations relate to an apparatus to support providing a computing service to a client including transferring control between a primary data processing system and a secondary data processing system in response to an event; the primary data processing system comprising a processor and associated memory and the secondary data processing system comprising a processor and associated memory; the apparatus comprising: circuitry to identify restoration data; the restoration data comprising at least data associated with at least one predetermined type of memory operation of the memory associated with the primary data processing system, and circuitry to output any identified restoration data for storage in the memory associated with the processor of the secondary data processing system.
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公开(公告)号：US20190114241A1
公开(公告)日：2019-04-18
申请号：US16215252
申请日：2018-12-10
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Andrew R. Wheeler , Gregg B. Lesartre
Abstract: A node for a computing system may include a memory module, a main node processor and a management processor. The memory module may include a non-volatile memory, a module memory controller having a main bus interface for connection to a main bus and a management device providing access to the nonvolatile memory through a sideband management bus. The main node processor is connected to the module memory controller and has a main bus interface for connection to a main. The management processor has a side band interface for connection to the side band management bus. The side band management processor detects a failure of the node and, in response thereto, copies data from the non-volatile memory of the memory module to another node across the side band management bus.
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公开(公告)号：US10657016B2
公开(公告)日：2020-05-19
申请号：US16215252
申请日：2018-12-10
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Andrew R. Wheeler , Gregg B. Lesartre
Abstract: A node for a computing system may include a memory module, a main node processor and a management processor. The memory module may include a non-volatile memory, a module memory controller having a main bus interface for connection to a main bus and a management device providing access to the non-volatile memory through a sideband management bus. The main node processor is connected to the module memory controller and has a main bus interface for connection to a main bus. The management processor has a sideband interface for connection to the sideband management bus. The sideband management processor detects a failure of the node and, in response thereto, copies data from the non-volatile memory of the memory module to another node across the sideband management bus.
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公开(公告)号：US20190334771A1
公开(公告)日：2019-10-31
申请号：US15967583
申请日：2018-04-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Dejan S Milojicic , Sharad Singhal , Andrew R. Wheeler , Michael S. Woodacre
IPC: H04L12/24 , G06F11/34 , G06F11/30 , H04L12/26 , H04L12/911
Abstract: Systems and methods for dynamically and programmatically controlling hardware and software to optimize bandwidth and latency across partitions in a computing system are discussed herein. In various embodiments, performance within a partitioned computing system may be monitored and used to automatically reconfigure the computing system to optimize aggregate bandwidth and latency. Reconfiguring the computing system may comprise reallocating hardware resources among partitions, programming firewalls to enable higher bandwidth for specific inter-partition traffic, switching programming models associated with individual partitions, starting additional instances of one or more applications running on the partitions, and/or one or more other operations to optimize the overall aggregate bandwidth and latency of the system.
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