公开(公告)号：US10558569B2

公开(公告)日：2020-02-11

申请号：US15031805

申请日：2013-10-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Hans Boehm ,  Dhruva Chakrabarti

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/0804 ,  G06F11/30 ,  G06F12/02 ,  G06F12/0806 ,  G06F12/128

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to control a cache. An example method includes monitoring cache lines in a cache, the cache lines storing recently written data to the cache, the recently written data corresponding to main memory, comparing a total quantity of the cache lines to a threshold that is less than a cache line storage capacity of the cache, and causing a write back of at least one of the cache lines to the main memory when a store event causes the total quantity of the cache lines to satisfy the threshold.

公开(公告)号：US20160246724A1

公开(公告)日：2016-08-25

申请号：US15031805

申请日：2013-10-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Hans Boehm ,  Dhruva Chakrabarti

IPC: G06F12/08 ,  G06F12/02 ,  G06F12/12

CPC classification number: G06F12/0833 ,  G06F11/3037 ,  G06F12/0238 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/128 ,  G06F2201/81 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/202 ,  G06F2212/621

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to control a cache. An example method includes monitoring cache lines in a cache, the cache lines storing recently written data to the cache, the recently written data corresponding to main memory, comparing a total quantity of the cache lines to a threshold that is less than a cache line storage capacity of the cache, and causing a write back of at least one of the cache lines to the main memory when a store event causes the total quantity of the cache lines to satisfy the threshold.

Abstract translation: 公开了方法，装置，系统和制品以控制高速缓存。 示例性方法包括监视高速缓存中的高速缓存行，将高速缓存行存储到高速缓存的最近写入的数据，最近写入的与主存储器相对应的数据，将高速缓存行的总量与小于高速缓存行存储器的阈值进行比较 高速缓存的容量，并且当存储事件导致高速缓存行的总量满足阈值时，使至少一条高速缓存行写回主存储器。

公开(公告)号：US20170192886A1

公开(公告)日：2017-07-06

申请号：US15325255

申请日：2014-07-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Hans Boehm ,  Naveen Muralimanohar

IPC: G06F12/0804 ,  G06F12/0815

Abstract: A coherence logic of a first core in a multi-core processor receives a request to send a cache line to a second core in the multi-core processor. In response to receiving the request, the coherence logic determines if the cache line is associated to a logically nonvolatile virtual page mapped to a nonvolatile physical page in a nonvolatile main memory. If so, the coherence logic flushes the cache line from the cache to the nonvolatile main memory and then sends the cache line to the second core.