公开(公告)号：US10333516B2

公开(公告)日：2019-06-25

申请号：US15749370

申请日：2015-07-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Cheng Li ,  Kunzhi Yu ,  Marco Fiorentino ,  Raymond G Beausoleil

IPC: H04B10/00 ,  H03K17/78 ,  H03F3/08 ,  G01J1/44 ,  H03K17/94 ,  H04B10/69

Abstract: In one example, a device includes a photodetector to generate an electrical signal in response to an optical signal and a transimpedance amplifier unit to receive the electrical signal. In one example, the transimpedance amplifier unit may include a first inverter unit, a second inverter unit coupled to the first inverter unit, and a third inverter unit coupled to the second inverter unit. In one example the third inverter unit may include a feedback resistor and a first n-type transistor in parallel to the feedback resistor, where the first n-type transistor is to provide a variable gain of the third inverter unit.

公开(公告)号：US09917713B2

公开(公告)日：2018-03-13

申请号：US15139779

申请日：2016-04-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Kunzhi Yu ,  Cheng Li ,  Marco Fiorentino ,  Raymond G. Beausoleil

IPC: H03D1/00 ,  H04L27/22 ,  H04L27/233 ,  H04L25/06

CPC classification number: H04L27/223 ,  H04L7/033 ,  H04L25/066 ,  H04L25/069 ,  H04L27/2338

Abstract: In one example, an apparatus includes an offset tunable edge slicer having an input to receive a pulse amplitude modulation signal. The offset tunable edge slicer also has a plurality of possible offset settings corresponding to a plurality of different reference voltages of the offset tunable edge slicer. A multiplexer has an output coupled to the input of the offset tunable edge slicer and an input to receive a control signal that selects one of the plurality of possible offset settings for the offset tunable edge slicer. A phase detector has an input coupled to an output of the offset tunable edge slicer.

公开(公告)号：US10673535B2

公开(公告)日：2020-06-02

申请号：US16085364

申请日：2016-04-14

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Cheng Li ,  Kunzhi Yu ,  Marco Fiorentino ,  Raymond G. Beausoleil

IPC: H04B10/69 ,  H04B10/516 ,  H04B10/63 ,  H04L25/49

Abstract: An example optical receiver may have an optical receiver front-end, four slicers, and a logic block. The optical receiver front-end may include a transimpedance amplifier to convert a photodiode output signal to a voltage signal. Three of the slicers may be data slicers, and one of the slicers may be an edge slicer. The slicers may each: shift the voltage signal based on an offset voltage set for the respective slicer, determine whether the shifted voltage signal is greater than a threshold value and generate a number of comparison signals based on the determining, and generate multiple digital signals by demuxing the comparison signals. The logic block may perform PAM-4 to binary decoding based on the data signals output by the data slicers and clock-and-data-recovery based on the digital signals output by the edge slicer.

公开(公告)号：US20190089466A1

公开(公告)日：2019-03-21

申请号：US16085364

申请日：2016-04-14

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Cheng Li ,  Kunzhi Yu ,  Marco Fiorentino ,  Raymond G. Beausoleil

IPC: H04B10/69 ,  H04B10/63 ,  H04B10/516 ,  H04L25/49

CPC classification number: H04B10/6931 ,  H04B10/5161 ,  H04B10/63 ,  H04B10/695 ,  H04L25/4917

Abstract: An example optical receiver may have an optical receiver front-end, four slicers, and a logic block. The optical receiver front-end may include a transimpedance amplifier to convert a photodiode output signal to a voltage signal. Three of the slicers may be data slicers, and one of the slicers may be an edge slicer. The slicers may each: shift the voltage signal based on an offset voltage set for the respective slicer, determine whether the shifted voltage signal is greater than a threshold value and generate a number of comparison signals based on the determining, and generate multiple digital signals by demuxing the comparison signals. The logic block may perform PAM-4 to binary decoding based on the data signals output by the data slicers and clock-and-data-recovery based on the digital signals output by the edge slicer.

公开(公告)号：US20170317865A1

公开(公告)日：2017-11-02

申请号：US15139779

申请日：2016-04-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Kunzhi Yu ,  Cheng Li ,  Marco Fiorentino ,  Raymond G. Beausoleil

IPC: H04L27/22 ,  H04L27/233

CPC classification number: H04L27/223 ,  H04L7/033 ,  H04L25/066 ,  H04L25/069 ,  H04L27/2338

Abstract: In one example, an apparatus includes an offset tunable edge slicer having an input to receive a pulse amplitude modulation signal. The offset tunable edge slicer also has a plurality of possible offset settings corresponding to a plurality of different reference voltages of the offset tunable edge slicer. A multiplexer has an output coupled to the input of the offset tunable edge slicer and an input to receive a control signal that selects one of the plurality of possible offset settings for the offset tunable edge slicer. A phase detector has an input coupled to an output of the offset tunable edge slicer.