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    Optical logic gates
    2.
    发明授权
    Optical logic gates 有权

    公开(公告)号：US10386698B2

    公开(公告)日：2019-08-20

    申请号：US15565281

    申请日：2015-05-08

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Charles M. Santori ,  Jason Pelc ,  Ranojoy Bose ,  Cheng Li ,  Raymond G Beausoleil

    IPC: G02F3/00 ,  G02F1/35 ,  G02F3/02 ,  G02B6/12

    Abstract: In the examples provided herein, an optical logic gate includes multiple couplers, where no more than two types of couplers are used in the optical logic gate, and further wherein the two types of couplers consist of: a 3-dB coupler and a weak coupler with a given transmission-to-reflection ratio. The optical logic gate also includes a first resonator, wherein the first resonator comprises a photonic crystal resonator or a nonlinear ring resonator, wherein in operation, the first resonator has a dedicated continuous wave input to bias a complex amplitude of a total field input to the first resonator such that the total field input is either above or below a nonlinear switching threshold of the first resonator, where the optical logic gate is an integrated photonic circuit.

    RECEIVERS WITH AUTOMATIC GAIN CONTROL
    3.
    发明申请
    RECEIVERS WITH AUTOMATIC GAIN CONTROL 审中-公开

    公开(公告)号：US20190068292A1

    公开(公告)日：2019-02-28

    申请号：US15768975

    申请日：2015-10-29

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Kehan Zhu ,  Cheng Li ,  Marco Florentino

    IPC: H04B10/69 ,  H04B10/25 ,  H04L25/49

    CPC classification number: H04B10/6931 ,  H04B10/25 ,  H04B10/2507 ,  H04B10/693 ,  H04L25/4917

    Abstract: One example of a receiver includes a first stage, a second stage, a third stage, and an automatic gain controller. The first stage amplifies an input signal to provide a first signal. The second stage amplifies or attenuates the first signal to provide a second signal based on a tunable gain of the second stage. The tunable gain is adjusted in response to a differential signal. The third stage amplifies the second signal to provide an output signal. The automatic gain controller provides the differential signal based on a comparison between a peak voltage of the output signal and the sum of a common mode voltage of the output signal and an offset voltage.

    OPTICAL SIGNAL MODULATION
    4.
    发明申请
    OPTICAL SIGNAL MODULATION 审中-公开

    公开(公告)号：US20190020416A1

    公开(公告)日：2019-01-17

    申请号：US16068713

    申请日：2016-01-15

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Tsung-Ching Huang ,  Ashkan Seyedi ,  Chin-Hui Chen ,  Cheng Li ,  Marco Fiorentino ,  Raymond G. Beausoleil

    IPC: H04B10/516 ,  H04J14/02

    Abstract: An example system includes an optical modulator and a multiplexing controller. The modulator includes a data bus for receiving at least one data signal, a plurality of multiplexers and a plurality of modulating segments. Each multiplexer is coupled to the data bus to receive at least one data signal and to output a multiplexed signal. Each modulating segment may receive the multiplexed signal from one of the plurality of multiplexers and modulate the multiplexed signal using an optical input. The multiplexing controller may be in communication with the plurality of multiplexers and may configure each of the plurality of multiplexers in accordance with a selected modulation type.

    OPTICAL MODULATOR DRIVERS
    5.
    发明申请
    OPTICAL MODULATOR DRIVERS 审中-公开

    公开(公告)号：US20180314080A1

    公开(公告)日：2018-11-01

    申请号：US15768901

    申请日：2015-10-28

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Nan Qi ,  Cheng Li ,  Marco Fiorentino

    IPC: G02F1/01 ,  H04B10/588 ,  G02F1/21

    CPC classification number: H04B10/588 ,  G02F1/0327 ,  G02F1/225 ,  G02F2201/126

    Abstract: One example of a system includes an optical modulator, a push-pull driver, and a compensation circuit. The optical modulator has a nonlinear capacitance. The push-pull driver is electrically coupled across the optical modulator. The push-pull driver charges the capacitance in response to a logic ‘1’ of a level-shifted differential signal and discharges the capacitance in response to a logic ‘0’ of the level-shifted differential signal. The compensation circuit increases the speed of the discharge of the capacitance in response to the level-shifted differential signal transitioning from a logic ‘1’ to a logic ‘0’.

    OPTICAL LOGIC GATES
    8.
    发明申请
    OPTICAL LOGIC GATES 审中-公开

    公开(公告)号：US20190353981A1

    公开(公告)日：2019-11-21

    申请号：US16526973

    申请日：2019-07-30

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Charles M. Santori ,  Jason Pelc ,  Ranojoy Bose ,  Cheng Li ,  Raymond G. Beausoleil

    IPC: G02F3/00 ,  G02B6/12 ,  G02F3/02 ,  G02F1/35

    Abstract: In the examples provided herein, an optical logic gate includes multiple couplers, where no more than two types of couplers are used in the optical logic gate, and further wherein the two types of couplers consist of: a 3-dB coupler and a weak coupler with a given transmission-to-reflection ratio. The optical logic gate also includes a first resonator, wherein the first resonator comprises a photonic crystal resonator or a nonlinear ring resonator, wherein in operation, the first resonator has a dedicated continuous wave input to bias a complex amplitude of a total field input to the first resonator such that the total field input is either above or below a nonlinear switching threshold of the first resonator, where the optical logic gate is an integrated photonic circuit.

    Signal control for segmented modulators
    9.
    发明授权
    Signal control for segmented modulators 有权

    公开(公告)号：US10481462B2

    公开(公告)日：2019-11-19

    申请号：US15768893

    申请日：2015-10-27

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Nan Qi ,  Cheng Li ,  Marco Fiorentino

    IPC: G02F1/21 ,  H03K5/135 ,  H03K5/00 ,  H03M9/00

    Abstract: In example implementations, an apparatus includes a serializer, a re-timing buffer coupled to the serializer, and a plurality of segments coupled to the re-timing buffer. The plurality of segments may be used for controlling a timing of an electrical signal. Each one of the plurality of segments may include a segment serializer, a timing control coupled to the segment serializer and a driver coupled to the timing control. In addition, a phase clock may be coupled to the segment serializer and the timing control of each one of the plurality of segments.

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