公开(公告)号：US10936044B2

公开(公告)日：2021-03-02

申请号：US16064050

申请日：2015-12-21

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Reza Bacchus ,  Melvin Benedict ,  Eric L Pope

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/20 ,  G06F1/3225 ,  G06F1/3206 ,  G06F11/30 ,  G06F13/16 ,  G11C7/04

Abstract: An example memory device comprises at least one memory region; and a controller to determine exceeding of a throttling threshold and to throttle processing of access requests for the at least one memory region.

公开(公告)号：US10740264B1

公开(公告)日：2020-08-11

申请号：US16397050

申请日：2019-04-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Melvin K. Benedict ,  Reza Bacchus ,  Mujeeb Rehman

IPC: G06F13/16 ,  G06F3/06 ,  G06F13/42

Abstract: A synchronous differential memory interconnect may include a bidirectional differential data signal bus, a unidirectional differential command and address bus, and a differential clock signal. Memory read and write data may be transmitted over the data signal bus in a serial fashion.

公开(公告)号：US20210181829A1

公开(公告)日：2021-06-17

申请号：US17249392

申请日：2021-03-01

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Reza Bacchus ,  Melvin Benedict ,  Eric L. Pope

IPC: G06F1/3234 ,  G06F1/20 ,  G06F1/3225 ,  G06F1/3206 ,  G06F11/30 ,  G06F13/16

Abstract: An example memory device comprises at least one memory region; and a controller to determine exceeding of a throttling threshold and to throttle processing of access requests for the at least one memory region.