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公开(公告)号:US10936044B2
公开(公告)日:2021-03-02
申请号:US16064050
申请日:2015-12-21
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Reza Bacchus , Melvin Benedict , Eric L Pope
IPC: G06F1/00 , G06F1/3234 , G06F1/20 , G06F1/3225 , G06F1/3206 , G06F11/30 , G06F13/16 , G11C7/04
Abstract: An example memory device comprises at least one memory region; and a controller to determine exceeding of a throttling threshold and to throttle processing of access requests for the at least one memory region.
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公开(公告)号:US20160203065A1
公开(公告)日:2016-07-14
申请号:US14912130
申请日:2013-09-27
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Melvin K Benedict , Eric L Pope , Andrew C. Walton
CPC classification number: G06F11/2038 , G06F3/0619 , G06F3/0656 , G06F3/0683 , G06F11/1016 , G06F11/1446 , G06F11/2058 , G06F11/2069 , G06F2201/84 , G11C7/1012 , G11C7/1033 , G11C29/846
Abstract: Example implementations relate to using a spare memory on a memory module. In example implementations, a memory module may have a plurality of memories, including default memories and a spare memory. A plurality of data buffers on the memory module may select data nibbles from the plurality of memories such that when a default memory is identified as defective, a data nibble is selected from the spare memory and not from the defective default memory. A data nibble selected from the default memory may be in a first position in an output of the memory module when the default memory is functional. A data nibble selected from the spare memory may be in a second position in the output of the memory module.
Abstract translation: 示例实现涉及在存储器模块上使用备用存储器。 在示例实现中,存储器模块可以具有多个存储器,包括默认存储器和备用存储器。 存储器模块上的多个数据缓冲器可以从多个存储器中选择数据半字节,使得当将默认存储器识别为有缺陷时,从备用存储器中选择数据半字节,而不是从缺陷的默认存储器中选择数据半字节。 当默认存储器功能时,从默认存储器中选择的数据半字节可以处于存储器模块的输出中的第一位置。 从备用存储器中选择的数据半字节可以处于存储器模块的输出中的第二位置。
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公开(公告)号:US10725689B2
公开(公告)日:2020-07-28
申请号:US15752250
申请日:2015-08-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Melvin K Benedict , Eric L Pope
Abstract: In one example in accordance with the present disclosure, a system for backup of a physical memory region of volatile memory. The system may include: a non-volatile memory, a volatile memory, at least one processor to: execute an application that indicates a virtual memory region stored in the volatile memory, wherein the virtual memory region is associated with an application, determine a corresponding physical memory region of the volatile memory for backup based on the indicated virtual memory region, and at least one memory controller to: receive a backup signal for the physical memory region of the volatile memory, and responsive to receiving the backup signal, backup up the physical memory region of the volatile memory to a memory region of the non-volatile memory.
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公开(公告)号:US10453516B2
公开(公告)日:2019-10-22
申请号:US15899514
申请日:2018-02-20
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Reza M Bacchus , Melvin K Benedict , Stephen F Contreras , Eric L Pope , Chi K Sides , Chun-Pin Huang
IPC: G11C5/06 , G11C5/10 , G11C11/4074 , G11C5/14 , G11C5/04
Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. A sufficient number of stitching capacitors are to couple the first power plane to a second power plane.
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公开(公告)号:US10546649B2
公开(公告)日:2020-01-28
申请号:US15753315
申请日:2015-08-18
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Eric L Pope , Scott P Faasse
Abstract: In one example in accordance with the present disclosure, a method includes mapping, using post-package repair, an address associated with a first memory row of a computing device to a spare memory row of the computing device, wherein the spare memory row has a memory failure pattern, and reading data from the spare memory row.
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公开(公告)号:US20190019569A1
公开(公告)日:2019-01-17
申请号:US16066392
申请日:2016-01-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Eric L Pope
Abstract: Addresses of memory cells that have errors corrected by error correction operations are evaluated to identify a failed row of memory. Post package repair is implemented on the failed row.
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公开(公告)号:US10180888B2
公开(公告)日:2019-01-15
申请号:US14912130
申请日:2013-09-27
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Melvin K Benedict , Eric L Pope , Andrew C. Walton
Abstract: Example implementations relate to using a spare memory on a memory module. In example implementations, a memory module may have a plurality of memories, including default memories and a spare memory. A plurality of data buffers on the memory module may select data nibbles from the plurality of memories such that when a default memory is identified as defective, a data nibble is selected from the spare memory and not from the defective default memory. A data nibble selected from the default memory may be in a first position in an output of the memory module when the default memory is functional. A data nibble selected from the spare memory may be in a second position in the output of the memory module.
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