公开(公告)号：US07342971B2

公开(公告)日：2008-03-11

申请号：US10666825

申请日：2003-09-16

申请人： Harvey L. Berger ,  Gerald R. Fischer

发明人： Harvey L. Berger ,  Gerald R. Fischer

IPC分类号： H04L27/00

CPC分类号： H04B1/7176 ,  H04B1/69

摘要： A method for ultra wideband (UWB) communication in which UWB pulses encode binary data as either normal or inverted (anti-podal) pulses. In the case of pulses of a carrier signal, each pulse has the carrier signal either inverted or in phase, that is, shifted by 180°, or not. For example, a binary “1” may be encoded as a normal or non-inverted pulse and a binary “0” as an inverted pulse. After each carrier pulse is rectified and filtered, detection is effected using a threshold value of zero, resulting in increased immunity to noise, compared with detection of unidirectional pulses. In one aspect of the invention, data pertaining to multiple communication channels are encoded in time-divided portions of each UWB pulse.

摘要翻译： 一种超宽带（UWB）通信的方法，其中UWB脉冲将二进制数据编码为正常或反向（反荚果）脉冲。 在载波信号的脉冲的情况下，每个脉冲具有反相或同相的载波信号，即偏移180°。 例如，二进制“1”可以被编码为正常或非反相脉冲，二进制“0”被编码为反相脉冲。 在每个载波脉冲被整流和滤波之后，与单向脉冲的检测相比，使用零值的阈值进行检测，导致增加的抗噪声能力。 在本发明的一个方面中，关于多个通信信道的数据被编码在每个UWB脉冲的时分部分中。

公开(公告)号：US06563389B1

公开(公告)日：2003-05-13

申请号：US10001714

申请日：2001-10-24

申请人： Gerald R. Fischer

发明人： Gerald R. Fischer

IPC分类号： H03L700

CPC分类号： H03L7/107 ,  H03L7/18

摘要： A phase locked loop (10) for generating an output frequency signal. The phase locked loop (10) includes a controlled oscillator (14) to generate the output frequency signal in response to a tune signal. A phase detector (18) generates an error signal representing a difference between a reference frequency signal and the output frequency signal. A loop filter (12) having a filter characteristic, filters the error signal and generates the tune signal. The loop filter (12) includes a bandwidth switching circuit (19) to vary the filter characteristics. A charge cancellation circuit (22) is coupled to the loop filter (12). In response to the error signal, the charge cancellation circuit (22) cancels errors associated with the bandwidth switching circuit.

摘要翻译： 一种用于产生输出频率信号的锁相环（10）。 锁相环（10）包括受控振荡器（14），以响应于调谐信号产生输出频率信号。 相位检测器（18）产生表示基准频率信号与输出频率信号之间的差的误差信号。 具有滤波器特性的环路滤波器（12），对误差信号进行滤波并产生调谐信号。 环路滤波器（12）包括带宽切换电路（19）以改变滤波器特性。 电荷消除电路（22）耦合到环路滤波器（12）。 响应于误差信号，电荷消除电路（22）消除与带宽切换电路相关的误差。

公开(公告)号：US5051627A

公开(公告)日：1991-09-24

申请号：US459220

申请日：1989-12-29

申请人： Neal J. Schneier ,  Gerald R. Fischer ,  Roger A. Davidheiser ,  George E. Avera

发明人： Neal J. Schneier ,  Gerald R. Fischer ,  Roger A. Davidheiser ,  George E. Avera

IPC分类号： G11C11/44 ,  H03K19/195

CPC分类号： H03K19/1952 ,  Y10S505/858 ,  Y10S505/865

摘要： A family of logic circuits using nonhysteretic superconducting quantum interference devices (SQUIDs) connected together to perform various functions using a common operating principle. Each circuit has an output line, first and second power supply lines having first and second voltage states, and input lines that can have one of the two voltage states. A pull-up circuit, having at least one SQUID, is connected between the output line and the first power supply line, and the input lines are coupled to the pull-up circuit in such a manner as to pull the output line to the first voltage state only if the input lines conform with a selected combination of voltage states. A pull-down circuit, also having at least one SQUID, is connected between the output line and the second power supply line, to pull the output line to the second voltage state only when input lines do not conform with the selected combination of voltage states. A single configuration of SQUIDs can be connected to perform any of six different basic Boolean logic functions on signals applied to the input lines. Additional SQUIDs allow the performance of more complex logic functions. A slightly different arrangement of SQUIDs operates as a two-port random access memory cell.

公开(公告)号：US06784728B2

公开(公告)日：2004-08-31

申请号：US10209379

申请日：2002-07-31

申请人： Gerald R. Fischer

发明人： Gerald R. Fischer

IPC分类号： H04B110

CPC分类号： H03L7/107 ,  H03L7/18

摘要： A switched low pass filter (18) minimizes transients generated during filter switching events and eliminates active circuit random noise. The switched low pass filter (18) includes a filter input terminal (26) for receiving an input base band signal, and an RC circuit (R1, C1, S1, S2) for receiving the input base band signal and for passing only a filtered portion of the input base band signal depending on a wide, mid or narrow band mode of filter operation. The switched low pass filter (18) also includes a transient reduction circuit (34) in switchable communication with the RC circuit (R1, C1, S1, S2) for minimizing transients and switching events caused by transitioning to the mid and narrow band modes of filter operation.

公开(公告)号：US07929640B2

公开(公告)日：2011-04-19

申请号：US11559975

申请日：2006-11-15

申请人： Andrew Donovan Smith ,  Gerald R. Fischer

发明人： Andrew Donovan Smith ,  Gerald R. Fischer

IPC分类号： H04L27/20

CPC分类号： H04L27/2035 ,  H04L27/205

摘要： A plurality of differential encoders encodes a plurality of parallel data bit streams. XOR gates interleave the outputs of the differential encoders forming a single high speed differentially encoded bit stream with a data rate that is the sum of the data rate of the parallel data bit streams. The high speed data stream provides a single differentially encoded input to a differential phase shift keying modulator that generates symbols for a high speed optical communication system.

摘要翻译： 多个差分编码器对多个并行数据比特流进行编码。 XOR门将形成单个高速差分编码比特流的差分编码器的输出与作为并行数据比特流的数据速率之和的数据速率进行交织。 高速数据流向差分相移键控调制器提供单个差分编码的输入，该调制器产生用于高速光通信系统的符号。

公开(公告)号：US06680654B2

公开(公告)日：2004-01-20

申请号：US09999679

申请日：2001-10-24

申请人： Gerald R. Fischer ,  Talley J. Allen ,  Ken K. Tsai

发明人： Gerald R. Fischer ,  Talley J. Allen ,  Ken K. Tsai

IPC分类号： H03L7085

CPC分类号： H03L7/093 ,  H03L7/18

摘要： A phase locked loop (10) for generating a variable output frequency signal. The phase locked loop (10) includes a controlled oscillator (14) to generate the variable output frequency signal in response to a tune signal. A phase detector (18) is activable in response to a gating signal (20) to generate an error signal representing a difference between a reference frequency signal and the variable output frequency signal. A loop filter (12) having a filter characteristic, filters the error signal and generates the tune signal. An offset cancellation circuit (22) is coupled to the loop filter (12). In response to an error signal representing phase offset of the phase locked loop (10), the offset cancellation circuit (22) supplies a compensating signal to reduce the phase offset.

摘要翻译： 一种用于产生可变输出频率信号的锁相环（10）。 锁相环（10）包括受控振荡器（14），以响应于调谐信号产生可变输出频率信号。 相位检测器（18）可响应选通信号（20）而激活，以产生表示参考频率信号和可变输出频率信号之间的差的误差信号。 具有滤波器特性的环路滤波器（12），对误差信号进行滤波并产生调谐信号。 偏移消除电路（22）耦合到环路滤波器（12）。 响应于表示锁相环（10）的相位偏移的误差信号，偏移消除电路（22）提供补偿信号以减小相位偏移。

公开(公告)号：US06570457B2

公开(公告)日：2003-05-27

申请号：US10000613

申请日：2001-10-24

申请人： Gerald R. Fischer

发明人： Gerald R. Fischer

IPC分类号： H03L700

CPC分类号： H03L7/107 ,  H03L7/093 ,  H03L7/18 ,  H03L7/1974

摘要： The present invention provides a phase locked loop (10) for generating a variable output frequency signal. The phase locked loop (10) includes a controlled oscillator (14) to generate the variable output frequency signal in response to a tune signal. A feedback frequency divider (16) coupled to the controlled oscillator (14) is operable to generate a divided frequency signal from the variable output frequency signal. A phase detector (18) generates an error signal representing a difference between a reference frequency signal and the divided frequency signal. A sample and hold circuit (22) is activable in response to a gating signal (20) derived from the reference frequency, to sample the error signal and generate a sampled signal. A loop filter (12) filters the sampled signal and generates the tune signal.

摘要翻译： 本发明提供一种用于产生可变输出频率信号的锁相环（10）。 锁相环（10）包括受控振荡器（14），以响应于调谐信号产生可变输出频率信号。 耦合到受控振荡器（14）的反馈分频器（16）可操作以从可变输出频率信号产生分频信号。 相位检测器（18）产生表示基准频率信号和分频信号之间的差的误差信号。 响应于从参考频率导出的门控信号（20），采样和保持电路（22）可激活，以对误差信号进行采样并产生采样信号。 环路滤波器（12）对采样信号进行滤波并产生调谐信号。

公开(公告)号：US20080112507A1

公开(公告)日：2008-05-15

申请号：US11559975

申请日：2006-11-15

申请人： Andrew Donovan Smith ,  Gerald R. Fischer

发明人： Andrew Donovan Smith ,  Gerald R. Fischer

IPC分类号： H04L27/20

CPC分类号： H04L27/2035 ,  H04L27/205

摘要： A plurality of differential encoders encodes a plurality of parallel data bit streams. XOR gates interleave the outputs of the differential encoders forming a single high speed differentially encoded bit stream with a data rate that is the sum of the data rate of the parallel data bit streams. The high speed data stream provides a single differentially encoded input to a differential phase shift keying modulator that generates symbols for a high speed optical communication system.

摘要翻译： 多个差分编码器对多个并行数据比特流进行编码。 XOR门将形成单个高速差分编码比特流的差分编码器的输出与作为并行数据比特流的数据速率之和的数据速率进行交织。 高速数据流向差分相移键控调制器提供单个差分编码的输入，该调制器产生用于高速光通信系统的符号。